Subroutine Coverage
| blib/lib/Verilog/Netlist/Module.pm |
|
| Criterion |
Covered |
Total |
% |
| subroutine |
35 |
39 |
89.7
|
| pod |
24 |
29 |
82.7
|
| line |
count |
pod |
subroutine |
|
7
|
8 |
n/a |
BEGIN |
|
8
|
8 |
n/a |
BEGIN |
|
9
|
8 |
n/a |
BEGIN |
|
10
|
8 |
n/a |
BEGIN |
|
11
|
8 |
n/a |
BEGIN |
|
12
|
8 |
n/a |
BEGIN |
|
13
|
8 |
n/a |
BEGIN |
|
14
|
8 |
n/a |
BEGIN |
|
15
|
8 |
n/a |
BEGIN |
|
16
|
8 |
n/a |
BEGIN |
|
60
|
204 |
No |
delete |
|
81
|
0 |
Yes |
logger |
|
85
|
239 |
Yes |
modulename_from_filename |
|
92
|
26 |
Yes |
find_port |
|
97
|
17 |
Yes |
find_port_by_index |
|
107
|
452 |
Yes |
find_cell |
|
112
|
12720 |
Yes |
find_net |
|
120
|
0 |
No |
attrs_sorted |
|
123
|
337 |
Yes |
nets |
|
126
|
97 |
Yes |
nets_sorted |
|
129
|
337 |
Yes |
ports |
|
132
|
80 |
Yes |
ports_sorted |
|
135
|
1 |
Yes |
ports_ordered |
|
139
|
346 |
Yes |
cells |
|
142
|
79 |
Yes |
cells_sorted |
|
145
|
243 |
Yes |
statements |
|
148
|
69 |
Yes |
statements_sorted |
|
152
|
0 |
Yes |
nets_and_ports_sorted |
|
165
|
12572 |
Yes |
new_net |
|
191
|
0 |
No |
new_attr |
|
197
|
684 |
Yes |
new_port |
|
206
|
451 |
Yes |
new_cell |
|
226
|
6 |
No |
new_contassign |
|
242
|
4 |
No |
new_defparam |
|
258
|
54 |
Yes |
level |
|
272
|
94 |
Yes |
link |
|
286
|
39 |
Yes |
lint |
|
304
|
32 |
Yes |
verilog_text |
|
333
|
67 |
Yes |
dump |