File Coverage

blib/lib/Verilog/Netlist/Module.pm

Criterion	Covered	Total	%
statement	180	203	88.6
branch	18	28	64.2
condition	18	36	50.0
subroutine	35	39	89.7
pod	24	29	82.7
total	275	335	82.0

# Verilog - Verilog Perl Interface
# See copyright, etc in below POD section.
######################################################################

package Verilog::Netlist::Module;

use Verilog::Netlist;
use Verilog::Netlist::ContAssign;
use Verilog::Netlist::Defparam;
use Verilog::Netlist::Port;
use Verilog::Netlist::Net;
use Verilog::Netlist::Cell;
use Verilog::Netlist::Pin;
use Verilog::Netlist::Subclass;
use vars qw($VERSION @ISA);
use strict;
@ISA = qw(Verilog::Netlist::Module::Struct
	Verilog::Netlist::Subclass);

$VERSION = '3.480';

structs('new',
	'Verilog::Netlist::Module::Struct'
	=>[name     	=> '$', #'	# Name of the module
	   filename 	=> '$', #'	# Filename this came from
	   lineno	=> '$', #'	# Linenumber this came from
	   netlist	=> '$', #'	# Netlist is a member of
	   keyword	=> '$', #'	# Type of module
	   userdata	=> '%',		# User information
	   attributes	=> '%', #'	# Misc attributes for systemperl or other processors
	   #
	   attrs	=> '@',		# list of "category name[ =](.*)" strings
	   comment	=> '$', #'	# Comment provided by user
	   _ports	=> '%',		# hash of Verilog::Netlist::Ports
	   _portsordered=> '@',		# list of Verilog::Netlist::Ports as ordered in list of ports
	   _nets	=> '%',		# hash of Verilog::Netlist::Nets
	   _cells	=> '%',		# hash of Verilog::Netlist::Cells
	   _celldecls	=> '%',		# hash of declared cells (for autocell only)
	   _cellarray	=> '%',		# hash of declared cell widths (for autocell only)
	   _cellnum	=> '$',		# Number of next unnamed cell
	   _level	=> '$',		# Depth in hierarchy (if calculated)
	   _statements	=> '%',		# hash of Verilog::Netlist::ContAssigns
	   _stmtnum	=> '$',		# Number of next unnamed statement
	   is_top	=> '$', #'	# Module is at top of hier (not a child)
	   is_libcell	=> '$', #'	# Module is a library cell
	   # SystemPerl:
	   _autocovers  => '%', #'	# Hash of covers found in code
	   _autosignal	=> '$', #'	# Module has /*AUTOSIGNAL*/ in it
	   _autosubcells=> '$', #'	# Module has /*AUTOSUBCELL_DECL*/ in it
	   _autotrace	=> '%', #'	# Module has /*AUTOTRACE*/ in it
	   _autoinoutmod=> '$', #'	# Module has /*AUTOINOUT_MODULE*/ in it
	   _pintemplates=> '@', #'	# Module SP_TEMPLATEs
	   _ctor	=> '$', #'	# Module has SC_CTOR in it
	   _code_symbols=> '$', #'	# Hash ref of symbols found in raw code
	   _covergroups => '%', #'	# Hash of covergroups found in code
	   lesswarn     => '$',	#'	# True if some warnings should be disabled
	   ]);

sub delete {
    my $self = shift;
    foreach my $oref ($self->nets) {
	$oref->delete;
    }
    foreach my $oref ($self->ports) {
	$oref->delete;
    }
    foreach my $oref ($self->cells) {
	$oref->delete;
    }
    foreach my $oref ($self->statements) {
	$oref->delete;
    }
    my $h = $self->netlist->{_modules};
    delete $h->{$self->name};
    return undef;
}

######################################################################

sub logger {
    return $_[0]->netlist->logger;
}

sub modulename_from_filename {
    my $filename = shift;
    (my $module = $filename) =~ s/.*\///;
    $module =~ s/\.[a-z]+$//;
    return $module;
}

sub find_port {
    my $self = shift;
    my $search = shift;
    return $self->_ports->{$search} || $self->_ports->{"\\".$search." "};
}
sub find_port_by_index {
    my $self = shift;
    my $myindex = shift;
    # @{$self->_portsordered}[$myindex-1] returns the name of
    # the port in the module at this index.  Then, this is
    # used to find the port reference via the port hash
    my $name = @{$self->_portsordered}[$myindex-1];
    return undef if !$name;
    return $self->_ports->{$name};
}
sub find_cell {
    my $self = shift;
    my $search = shift;
    return $self->_cells->{$search} || $self->_cells->{"\\".$search." "};
}
sub find_net {
    my $self = shift;
    my $search = shift;
    my $rtn = $self->_nets->{$search}||"";
    #print "FINDNET ",$self->name, " SS $search  $rtn\n";
    return $self->_nets->{$search} || $self->_nets->{"\\".$search." "};
}

sub attrs_sorted {
    return (sort {$a cmp $b} @{$_[0]->attrs});
}
sub nets {
    return (values %{$_[0]->_nets});
}
sub nets_sorted {
    return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_nets}));
}
sub ports {
    return (values %{$_[0]->_ports});
}
sub ports_sorted {
    return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_ports}));
}
sub ports_ordered {
    my $self = shift;
    return map {$self->_ports->{$_}} @{$self->_portsordered};
}
sub cells {
    return (values %{$_[0]->_cells});
}
sub cells_sorted {
    return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_cells}));
}
sub statements {
    return (values %{$_[0]->_statements});
}
sub statements_sorted {
    return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_statements}));
}

sub nets_and_ports_sorted {
    my $self = shift;
    my @list = ($self->nets, $self->ports,);
    my @outlist; my $last = "";
    # Eliminate duplicates
    foreach my $e (sort {$a->name() cmp $b->name()} (@list)) {
	next if $e eq $last;
	push @outlist, $e;
	$last = $e;
    }
    return (@outlist);
}

sub new_net {
    my $self = shift;
    my %params = @_;

    # Create a new net under this
    my $netref;
    if (defined($params{msb})) {
	my $data_type;
	$data_type = "[".($params{msb});
	$data_type .= ":".($params{lsb}) if defined $params{lsb};
	$data_type .= "]";
	$netref = new Verilog::Netlist::Net(decl_type=>'net',
					    net_type => 'wire',
					    data_type => $data_type,
					    %params,
					    module => $self);
    } else {
	$netref = new Verilog::Netlist::Net(decl_type => 'net',
					    net_type => 'wire',
					    %params,
					    module => $self);
    }
    $self->_nets($netref->name(), $netref);
    return $netref;
}

sub new_attr {
    my $self = shift;
    my $clean_text = shift;
    push @{$self->attrs}, $clean_text;
}

sub new_port {
    my $self = shift;
    # @_ params
    # Create a new port under this module
    my $portref = new Verilog::Netlist::Port(@_, module=>$self,);
    $self->_ports($portref->name(), $portref);
    return $portref;
}

sub new_cell {
    my $self = shift;
    my %params = @_; # name=>, filename=>, lineno=>, submodname=>, params=>
    # Create a new cell under this module
    if (!defined $params{name} || $params{name} eq '') {
	# Blank instance name; invent a new one; use the next instance number in this module t$
	$self->_cellnum(($self->_cellnum||0) + 1);
	$params{name} = '__unnamed_instance_' . $self->_cellnum;
    }
    if (my $preexist = $self->find_cell($params{name})) {
	$self->_cellnum(($self->_cellnum||0) + 1);
	$params{name} .= '__duplicate_' . $self->_cellnum;
    }
    # Create a new cell; pass the potentially modified options
    my $cellref = new Verilog::Netlist::Cell(%params, module=>$self,);
    # Add the new cell to the hash of cells in this module
    $self->_cells($params{name}, $cellref);
    return $cellref;
}

sub new_contassign {
    my $self = shift;
    my %params = @_; # name=>, filename=>, lineno=>, keyword=> etc
    # Create a new statement under this module
    if (!defined $params{name} || $params{name} eq '') {
	# Blank instance name; invent a new one; use the next instance number in this module t$
	$self->_stmtnum(($self->_stmtnum||0) + 1);
	$params{name} = '__unnamed_statement_' . $self->_stmtnum;
    }
    # Create a new object; pass the potentially modified options
    my $newref = new Verilog::Netlist::ContAssign(%params, module=>$self,);
    # Add the new object to the hash of statements in this module
    $self->_statements($params{name}, $newref);
    return $newref;
}

sub new_defparam {
    my $self = shift;
    my %params = @_; # name=>, filename=>, lineno=>, keyword=> etc
    # Create a new statement under this module
    if (!defined $params{name} || $params{name} eq '') {
	# Blank instance name; invent a new one; use the next instance number in this module t$
	$self->_stmtnum(($self->_stmtnum||0) + 1);
	$params{name} = '__unnamed_statement_' . $self->_stmtnum;
    }
    # Create a new object; pass the potentially modified options
    my $newref = new Verilog::Netlist::Defparam(%params, module=>$self,);
    # Add the new object to the hash of statements in this module
    $self->_statements($params{name}, $newref);
    return $newref;
}

sub level {
    my $self = shift;
    my $level = $self->_level;
    return $level if defined $level;
    $self->_level(1);  # Set before recurse in case there's circular module refs
    foreach my $cell ($self->cells) {
	if ($cell->submod) {
	    my $celllevel = $cell->submod->level;
	    $self->_level($celllevel+1) if $celllevel >= $self->_level;
	}
    }
    return $self->_level;
}

sub link {
    my $self = shift;
    # Ports create nets, so link ports before nets
    foreach my $portref ($self->ports) {
	$portref->_link();
    }
    foreach my $netref ($self->nets) {
	$netref->_link();
    }
    foreach my $cellref ($self->cells) {
	$cellref->_link();
    }
}

sub lint {
    my $self = shift;
    if ($self->netlist->{use_vars}) {
	foreach my $portref ($self->ports) {
	    $portref->lint();
	}
	foreach my $netref ($self->nets) {
	    $netref->lint();
	}
    }
    foreach my $cellref ($self->cells) {
	$cellref->lint();
    }
    foreach my $oref ($self->statements) {
	$oref->lint();
    }
}

sub verilog_text {
    my $self = shift;
    my @out = ($self->keyword||'module')." ".$self->name." (\n";
    my $indent = "   ";
    # Port list
    my $comma="";
    push @out, $indent;
    foreach my $portref ($self->ports_sorted) {
	push @out, $comma, $portref->verilog_text;
	$comma = ", ";
    }
    push @out, ");\n";

    # Signal list
    foreach my $netref ($self->nets_sorted) {
	push @out, $indent, $netref->verilog_text, "\n";
    }
    # Cell list
    foreach my $cellref ($self->cells_sorted) {
	push @out, $indent, $cellref->verilog_text, "\n";
    }
    foreach my $oref ($self->statements_sorted) {
	push @out, $indent, $oref->verilog_text, "\n";
    }

    push @out, "end".($self->keyword||'module')."\n";
    return (wantarray ? @out : join('',@out));
}

sub dump {
    my $self = shift;
    my $indent = shift||0;
    my $norecurse = shift;
    print " "x$indent,"Module:",$self->name(),"  Kwd:",($self->keyword||''),"  File:",$self->filename(),"\n";
    if (!$norecurse) {
	foreach my $portref ($self->ports_sorted) {
	    $portref->dump($indent+2);
	}
	foreach my $netref ($self->nets_sorted) {
	    $netref->dump($indent+2);
	}
	foreach my $cellref ($self->cells_sorted) {
	    $cellref->dump($indent+2);
	}
	foreach my $cellref ($self->statements_sorted) {
	    $cellref->dump($indent+2);
	}
    }
}

######################################################################
#### Package return
1;
__END__