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package Verilog::VCD::Writer::Signal; |
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$Verilog::VCD::Writer::Signal::VERSION = '0.002'; |
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use strict; |
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use warnings; |
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use DateTime; |
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# ABSTRACT: Signal abstraction layer for Verilog::VCD::Writer |
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use Verilog::VCD::Writer::Symbol; |
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use v5.10; |
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use Moose; |
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use namespace::clean; |
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has name=>(is=>'ro',required=>1); |
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has type=>(is=>'ro',default=>'wire'); |
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has bitmax=>(is=>'ro'); |
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has bitmin=>(is=>'ro'); |
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has width=>(is=>'ro',lazy=>1,builder=>"_getWidth"); |
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has symbol=>(is=>'ro',builder=>"_getSymbol"); |
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sub _getSymbol{ |
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my $symTable=Verilog::VCD::Writer::Symbol->instance(); |
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return $symTable->symbol; |
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} |
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sub _getWidth{ |
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my $self=shift; |
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return 1 if (not defined $self->bitmax or not defined $self->bitmin); |
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return 1+$self->bitmax-$self->bitmin if($self->bitmax>$self->bitmin); |
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return 1+$self->bitmin - $self->bitmax; |
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} |
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sub printScope { |
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my ($self,$fh)=@_; |
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my $bus=''; |
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$bus="[$self->{bitmax}:$self->{bitmin}]" if(defined $self->bitmax and defined $self->bitmin); |
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say $fh join(' ',('$var ', $self->{type},$self->width,$self->{symbol},$self->{name},$bus,'$end')) ; |
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} |
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1 |
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__END__ |
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=pod |
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=encoding UTF-8 |
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=head1 NAME |
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Verilog::VCD::Writer::Signal - Signal abstraction layer for Verilog::VCD::Writer |
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=head1 VERSION |
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version 0.002 |
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=head1 SYNOPSIS |
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use Verilog::VCD::Writer; |
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use Verilog::VCD::Writer::Signal; |
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# my $signal=Verilog::VCD::Signal( |
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# name=>'signalName', |
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# type=> 'wire' |
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# bitmax=>7, |
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# bitmin=>0) |
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=head1 DESCRIPTION |
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This module is designed to be called from the Verilog::VCD::Writer::Module module. |
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=head1 INTERFACE |
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=head1 DEPENDENCIES |
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=head1 SEE ALSO |
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=for Pod::Coverage *EVERYTHING* |
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=head1 AUTHOR |
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82
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Vijayvithal Jahagirdar<jvs@cpan.org> |
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=head1 COPYRIGHT AND LICENSE |
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This software is copyright (c) 2017 by Vijayvithal. |
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This is free software; you can redistribute it and/or modify it under |
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the same terms as the Perl 5 programming language system itself. |
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=cut |