File Coverage

blib/lib/Verilog/VCD/Writer/Signal.pm
Criterion Covered Total %
statement 30 30 100.0
branch 6 6 100.0
condition 4 6 66.6
subroutine 10 10 100.0
pod 0 1 0.0
total 50 53 94.3


line stmt bran cond sub pod time code
1             package Verilog::VCD::Writer::Signal;
2             $Verilog::VCD::Writer::Signal::VERSION = '0.002';
3 4     4   55278 use strict;
  4         10  
  4         115  
4 4     4   22 use warnings;
  4         10  
  4         95  
5 4     4   710 use DateTime;
  4         478990  
  4         100  
6              
7             # ABSTRACT: Signal abstraction layer for Verilog::VCD::Writer
8 4     4   1683 use Verilog::VCD::Writer::Symbol;
  4         19  
  4         168  
9 4     4   75 use v5.10;
  4         15  
10 4     4   27 use Moose;
  4         15  
  4         31  
11 4     4   28802 use namespace::clean;
  4         11  
  4         39  
12             has name=>(is=>'ro',required=>1);
13             has type=>(is=>'ro',default=>'wire');
14             has bitmax=>(is=>'ro');
15             has bitmin=>(is=>'ro');
16             has width=>(is=>'ro',lazy=>1,builder=>"_getWidth");
17             has symbol=>(is=>'ro',builder=>"_getSymbol");
18              
19              
20              
21              
22             sub _getSymbol{
23 15     15   11499 my $symTable=Verilog::VCD::Writer::Symbol->instance();
24 15         5204 return $symTable->symbol;
25             }
26             sub _getWidth{
27 19     19   40 my $self=shift;
28 19 100 66     625 return 1 if (not defined $self->bitmax or not defined $self->bitmin);
29 9 100       346 return 1+$self->bitmax-$self->bitmin if($self->bitmax>$self->bitmin);
30 3         104 return 1+$self->bitmin - $self->bitmax;
31             }
32              
33              
34             sub printScope {
35 19     19 0 46 my ($self,$fh)=@_;
36 19         39 my $bus='';
37 19 100 66     596 $bus="[$self->{bitmax}:$self->{bitmin}]" if(defined $self->bitmax and defined $self->bitmin);
38 19         785 say $fh join(' ',('$var ', $self->{type},$self->width,$self->{symbol},$self->{name},$bus,'$end')) ;
39             }
40              
41             1
42              
43             __END__
44              
45             =pod
46              
47             =encoding UTF-8
48              
49             =head1 NAME
50              
51             Verilog::VCD::Writer::Signal - Signal abstraction layer for Verilog::VCD::Writer
52              
53             =head1 VERSION
54              
55             version 0.002
56              
57             =head1 SYNOPSIS
58              
59             use Verilog::VCD::Writer;
60             use Verilog::VCD::Writer::Signal;
61              
62             # my $signal=Verilog::VCD::Signal(
63             # name=>'signalName',
64             # type=> 'wire'
65             # bitmax=>7,
66             # bitmin=>0)
67              
68             =head1 DESCRIPTION
69              
70             This module is designed to be called from the Verilog::VCD::Writer::Module module.
71              
72             =head1 INTERFACE
73              
74             =head1 DEPENDENCIES
75              
76             =head1 SEE ALSO
77              
78             =for Pod::Coverage *EVERYTHING*
79              
80             =head1 AUTHOR
81              
82             Vijayvithal Jahagirdar<jvs@cpan.org>
83              
84             =head1 COPYRIGHT AND LICENSE
85              
86             This software is copyright (c) 2017 by Vijayvithal.
87              
88             This is free software; you can redistribute it and/or modify it under
89             the same terms as the Perl 5 programming language system itself.
90              
91             =cut