blib/lib/Verilog/VCD/Writer/Signal.pm | |||
---|---|---|---|
Criterion | Covered | Total | % |
branch | 6 | 6 | 100.0 |
line | true | false | branch |
---|---|---|---|
28 | 10 | 9 | unless defined $self->bitmax and defined $self->bitmin |
29 | 6 | 3 | if $self->bitmax > $self->bitmin |
37 | 9 | 10 | if defined $self->bitmax and defined $self->bitmin |