blib/lib/Verilog/VCD/Writer/Signal.pm | |||
---|---|---|---|
Criterion | Covered | Total | % |
condition | 4 | 6 | 66.6 |
line | !l | l&&!r | l&&r | condition |
---|---|---|---|---|
28 | 10 | 9 | 0 | defined $self->bitmax and defined $self->bitmin |
37 | 10 | 0 | 9 | defined $self->bitmax and defined $self->bitmin |