Branch Coverage

blib/lib/Verilog/VCD.pm
Criterion Covered Total %
branch 78 78 100.0


line true false branch
31 2 4 unless (defined $file)
50 2 31 unless (defined $file)
55 26 5 if ($opt)
56 3 23 unless (ref $opt eq 'HASH')
62 4 24 exists $opt->{'only_sigs'} ? :
66 6 22 if (exists $opt->{'siglist'}) { }
68 1 5 unless (%usigs)
77 7 20 exists $opt->{'use_stdout'} ? :
79 2 25 unless open my $fh, '<', $file
87 382 247 if (s/ ^ \s* \$ (\w+) \s+ //x)
90 24 358 if ($keyword eq 'date') { }
24 334 elsif ($keyword eq 'version') { }
22 312 elsif ($keyword eq 'comment') { }
24 288 elsif ($keyword eq 'timescale') { }
82 206 elsif ($keyword eq 'scope') { }
82 124 elsif ($keyword eq 'upscope') { }
103 21 elsif ($keyword eq 'var') { }
116 16 87 if $type eq 'port' and $size ne '1'
124 63 40 if exists $usigs{$full_name} or $all_sigs
133 2 20 unless ($num_sigs)
134 1 1 if ($all_sigs) { }
143 2 18 if ($num_sigs > 1 and $use_stdout)
148 15 3 unless ($only_sigs)
157 2 444 if (s/ ^ \$ comment \s* //x)
161 3 443 if (s/ ^ \$ vcdclose \s* //x) { }
26 417 elsif (/ ^ \$ (dump \w+) /x) { }
136 281 elsif (/ ^ [#] (\d+) /x) { }
150 131 elsif (/ ^ ([01zx]) (.+) /xi or / ^ [br] (\S+) \s+ (.+) /xi) { }
96 35 elsif (/ ^ p /x) { }
175 114 36 if (exists $data{$code})
176 20 94 if ($use_stdout) { }
188 46 50 if (exists $data{$code})
189 7 39 if ($use_stdout) { }
213 312 75 if length $line
222 178 209 unless length $lines[-1]
234 11 13 if (exists $opt->{'timescale'}) { }
246 10 1 if ($tscale =~ / (\d+) \s* ([a-z]+) /xi) { }
266 9 1 if (exists $mults{$units}) { }
275 8 1 if (exists $mults{$new_units}) { }