File Coverage

blib/lib/Verilog/Netlist/Port.pm

Criterion	Covered	Total	%
statement	45	52	86.5
branch	19	26	73.0
condition	4	12	33.3
subroutine	10	13	76.9
pod	3	8	37.5
total	81	111	72.9

# Verilog - Verilog Perl Interface
# See copyright, etc in below POD section.
######################################################################

package Verilog::Netlist::Port;

use Verilog::Netlist;
use Verilog::Netlist::Subclass;
use vars qw($VERSION @ISA);
use strict;
@ISA = qw(Verilog::Netlist::Port::Struct
	Verilog::Netlist::Subclass);

$VERSION = '3.478';

structs('_new_base',
	'Verilog::Netlist::Port::Struct'
	=>[name     	=> '$', #'	# Name of the port
	   filename 	=> '$', #'	# Filename this came from
	   lineno	=> '$', #'	# Linenumber this came from
	   userdata	=> '%',		# User information
	   attributes	=> '%', #'	# Misc attributes for systemperl or other processors
	   #
	   direction	=> '$', #'	# Direction (in/out/inout)
	   data_type	=> '$', #'	# SystemVerilog Type (logic/integer etc)
	   comment	=> '$', #'	# Comment provided by user
	   array	=> '$', #'	# Vectorization
	   module	=> '$', #'	# Module entity belongs to
	   # below only after links()
	   net		=> '$', #'	# Net port connects
	   # below only after autos()
	   sp_autocreated	=> '$', #'	# Created by /*AUTOINOUT*/
	   ]);

sub new {
    my $class = shift;
    my %params = (@_);
    $params{data_type} = $params{type} if defined $params{type};  # Backward compatibility
    if ($params{direction}) {  # Correct common mistakes; plus the parser itself needs this conversion
	$params{direction} = 'in' if $params{direction} eq 'input';
	$params{direction} = 'out' if $params{direction} eq 'output';
    }
    return $class->_new_base(%params);
}

sub delete {
    my $self = shift;
    my $h = $self->module->_ports;
    delete $h->{$self->name};
    return undef;
}

######################################################################

sub netlist { return $_[0]->module->netlist; }

sub logger { return $_[0]->netlist->logger; }

sub type {  # Backward compatibility only
    my $self=shift;
    if ($#_ >= 0) { $self->data_type(@_); }
    return ($self->data_type || ($self->net && $self->net->type))||'';
}

sub _link {
    my $self = shift;
    if (!$self->net) {
	my $net = $self->module->find_net($self->name);
	if (!$net) {
	    my $msb;
	    my $lsb;
	    if (defined $self->data_type) {
		$self->data_type =~ /\[([^:]+)(:(.*))?\]$/;
		$msb = $1;
		$lsb = defined($3) ? $3 : $1;
	    }
	    $net = $self->module->new_net
		(name=>$self->name,
		 filename=>$self->filename, lineno=>$self->lineno,
		 decl_type=>"port", net_type=>"wire",
		 data_type=>$self->data_type, array=>$self->array,
		 comment=>undef, msb=>$msb, lsb=>$lsb,
		 );
	    $net->attributes($self->attributes);  # Copy attributes across
	}
	if ($net && $net->port && $net->port != $self) {
	    $self->error("Port redeclares existing port: ",$self->name,"\n");
	}
	$self->net($net);
	$self->net->port($self);
	# A input to the module is actually a "source" or thus "out" of the net.
	$self->net->_used_in_inc()    if ($self->direction() eq 'out');
	$self->net->_used_out_inc()   if ($self->direction() eq 'in');
	$self->net->_used_inout_inc() if ($self->direction() eq 'inout');
    }
}
sub lint {}

sub verilog_text {
    my $self = shift;
    return $self->name;
}

sub dump {
    my $self = shift;
    my $indent = shift||0;
    print " "x$indent,"Port:",$self->name(),"  Dir:",$self->direction()
	,"  DataT:",$self->data_type(),"  Array:",$self->array()||"","\n";
}

######################################################################
#### Package return
1;
__END__