| blib/lib/Verilog/Netlist/Pin.pm | |||
|---|---|---|---|
| Criterion | Covered | Total | % |
| condition | 20 | 26 | 76.9 |
| line | !l | l&&!r | l&&r | condition |
|---|---|---|---|---|
| 68 | 1 | 800 | 5 | $self->nets and $self->port |
| 156 | 0 | 17 | 34 | $portname and not $self->cell->byorder |
| 168 | 49 | 0 | 55 | $change and $self->_nets |
| 49 | 10 | 45 | $change and $self->_nets and $self->port | |
| 194 | 38 | 2 | 0 | not $self->port and $self->submod |
| 197 | 2 | 21 | 17 | $self->port and $self->nets |
| 206 | 0 | 11 | 6 | $net->{'net'} and $net->{'net'}->port |
| 209 | 3 | 3 | 0 | $netdir eq 'in' and $portdir eq 'out' |
| line | l | !l | condition |
|---|---|---|---|
| 252 | 40 | 0 | shift() || 0 |