| blib/lib/Verilog/Netlist/Cell.pm | |||
|---|---|---|---|
| Criterion | Covered | Total | % |
| condition | 18 | 25 | 72.0 |
| line | !l | l&&!r | l&&r | condition |
|---|---|---|---|---|
| 83 | 72 | 30 | 2 | not $self->submod and Verilog::Language::is_gateprim($self->submodname) |
| 86 | 74 | 0 | 30 | not $self->submod || $self->gateprim || $self->module->is_libcell and $self->netlist->{'link_read'} |
| 0 | 5 | 25 | not $self->submod || $self->gateprim || $self->module->is_libcell and $self->netlist->{'link_read'} and not $self->netlist->{'_missing_submod'}{$self->submodname} |
| line | l | !l | condition |
|---|---|---|---|
| 154 | 37 | 0 | shift() || 0 |
| 157 | 15 | 22 | $self->params || '' |
| line | l | !l&&r | !l&&!r | condition |
|---|---|---|---|---|
| 86 | 2 | 0 | 30 | $self->submod || $self->gateprim || $self->module->is_libcell |
| 122 | 35 | 1 | 3 | $self->submod or $self->gateprim |
| 1 | 3 | 0 | $self->submod or $self->gateprim or $self->netlist->{'link_read_nonfatal'} | |
| 185 | 2 | 0 | 0 | $self->_pins($name) || $self->_pins('\\' . $name . ' ') |