| blib/lib/Verilog/Netlist/Module.pm | |||
|---|---|---|---|
| Criterion | Covered | Total | % |
| condition | 18 | 36 | 50.0 |
| line | l | !l | condition |
|---|---|---|---|
| 114 | 120 | 12600 | $self->_nets->{$search} || '' |
| 211 | 0 | 0 | $self->_cellnum || 0 |
| 215 | 0 | 0 | $self->_cellnum || 0 |
| 231 | 5 | 1 | $self->_stmtnum || 0 |
| 247 | 0 | 4 | $self->_stmtnum || 0 |
| 305 | 32 | 0 | $self->keyword || 'module' |
| 328 | 32 | 0 | $self->keyword || 'module' |
| 334 | 30 | 37 | shift() || 0 |
| 336 | 67 | 0 | $self->keyword || '' |
| line | l | !l&&r | !l&&!r | condition |
|---|---|---|---|---|
| 94 | 26 | 0 | 0 | $self->_ports->{$search} || $self->_ports->{'\\' . $search . ' '} |
| 109 | 3 | 0 | 449 | $self->_cells->{$search} || $self->_cells->{'\\' . $search . ' '} |
| 116 | 120 | 0 | 12600 | $self->_nets->{$search} || $self->_nets->{'\\' . $search . ' '} |
| 209 | 0 | 0 | 451 | not defined $params{'name'} or $params{'name'} eq '' |
| 229 | 6 | 0 | 0 | not defined $params{'name'} or $params{'name'} eq '' |
| 245 | 4 | 0 | 0 | not defined $params{'name'} or $params{'name'} eq '' |