Subroutine Coverage

blib/lib/CPU/Emulator/Z80.pm
Criterion Covered Total %
subroutine 131 134 97.7
pod 12 12 100.0


line count pod subroutine
5 13 n/a BEGIN
6 13 n/a BEGIN
8 13 n/a BEGIN
16 13 n/a BEGIN
17 13 n/a BEGIN
18 13 n/a BEGIN
19 13 n/a BEGIN
20 13 n/a BEGIN
22 13 n/a BEGIN
23 13 n/a BEGIN
24 13 n/a BEGIN
25 13 n/a BEGIN
26 13 n/a BEGIN
27 13 n/a BEGIN
28 13 n/a BEGIN
104 1312 Yes new
142 0 n/a __ANON__
143 0 n/a __ANON__
144 0 n/a __ANON__
191 9177 n/a _derive_register16
194 7972 n/a __ANON__
198 7838 n/a __ANON__
207 10488 n/a _derive_register8
210 394 n/a __ANON__
216 246 n/a __ANON__
240 27 Yes add_input_device
248 42 n/a _get_from_input
268 10 Yes add_output_device
276 21 n/a _put_to_output
292 11488 Yes memory
306 124468 Yes register
318 3 Yes status
330 1 n/a _status_load
352 2 Yes registers
361 1283 Yes format_registers
729 2 Yes nmi
735 3 Yes interrupt
744 11 n/a _interrupts_enabled
750 1344 Yes run
779 2 Yes stopped
785 3070 n/a _fetch
821 1468 n/a _execute
843 10358 n/a _got_prefix
848 56 n/a _check_cond
862 20 n/a _ADD_r16_r16
871 4 n/a _ADC_r16_r16
873 15 n/a _ADC_r8_r8
875 30 n/a _ADD_r8_r8
881 192 n/a _RES
882 192 n/a _SET
884 384 n/a _RES_SET
913 200 n/a _BIT
935 45 n/a _binop
956 15 n/a _AND_r8_r8
957 15 n/a _OR_r8_r8
958 15 n/a _XOR_r8_r8
959 15 n/a _SBC_r8_r8
960 4 n/a _SBC_r16_r16
962 67 n/a _SUB_r8_r8
970 4 n/a _SUB_r16_r16
977 29 n/a _CP_r8_r8
990 20 n/a _DEC
1005 1 n/a _EXX
1012 12 n/a _DJNZ
1025 1 n/a _HALT
1027 21 n/a _INC
1033 26 n/a _LDI
1047 16 n/a _LDIR
1053 9 n/a _LDD
1061 8 n/a _LDDR
1067 14 n/a _CPI
1084 4 n/a _CPIR
1091 9 n/a _CPD
1098 8 n/a _CPDR
1104 1 n/a _RLD
1120 1 n/a _RRD
1136 6 n/a _JR_unconditional
1143 28 n/a _JP_unconditional
1146 19 n/a _CALL_unconditional
1150 8 n/a _LD_ind_r16
1154 22 n/a _LD_ind_r8
1158 425 n/a _LD_indHL_r8
1163 28 n/a _LD_indr16_r8
1168 60 n/a _LD_r16_imm
1173 42 n/a _LD_r8_imm
1180 8 n/a _LD_r16_ind
1184 28 n/a _LD_r8_indr16
1188 22 n/a _LD_r8_ind
1192 702 n/a _LD_r8_indHL
1197 9 n/a _LD_r16_r16
1201 542 n/a _LD_r8_r8
1221 1 n/a _LD_A_R
1222 1 n/a _LD_A_I
1224 2 n/a _LD_A_IR
1236 8 n/a _NEG
1241 26 n/a _NOP
1243 25 n/a _RLCA
1255 25 n/a _RRCA
1267 25 n/a _RLA
1278 25 n/a _RRA
1292 96 n/a _cb_rot
1318 24 n/a _RLC
1322 24 n/a _RRC
1326 24 n/a _RL
1337 24 n/a _RR
1346 24 n/a _SLA
1374 24 n/a _SLL
1404 24 n/a _SRA
1438 24 n/a _SRL
1474 2 n/a _DAA
1517 1 n/a _CPL
1525 4 n/a _SCF
1535 1 n/a _CCF
1545 30 n/a _POP
1552 32 n/a _PUSH
1560 8 n/a _IN_A_n
1566 30 n/a _IN_r_C
1580 1 n/a _OUT_n_A
1587 8 n/a _OUT_C_r
1594 1 n/a _OUT_C_0
1599 3 n/a _IND
1605 3 n/a _INI
1612 2 n/a _INDR
1618 2 n/a _INIR
1624 4 n/a _OUTD
1633 4 n/a _OUTI
1642 3 n/a _OTDR
1648 3 n/a _OTIR
1654 8 n/a _IM
1657 1 n/a _RETI
1660 7 n/a _RETN
1665 5 n/a _DI
1669 3 n/a _EI
1673 1634 n/a _swap_regs