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# You may distribute under the terms of either the GNU General Public License |
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# or the Artistic License (the same terms as Perl itself) |
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# |
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# (C) Paul Evans, 2022 -- leonerd@leonerd.org.uk |
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590057
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use v5.26; |
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use Object::Pad 0.57; |
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8740
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package Device::Chip::Si5351 0.01; |
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class Device::Chip::Si5351 |
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:isa(Device::Chip::Base::RegisteredI2C); |
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use Device::Chip::Base::RegisteredI2C 0.21; |
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use Carp; |
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use Future::AsyncAwait 0.38; |
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use Data::Bitfield qw( bitfield enumfield boolfield intfield ); |
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12027
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use POSIX qw( floor ); # TODO: grab this from builtin:: |
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37805
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# See also |
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# https://github.com/adafruit/Adafruit_Si5351_Library/blob/master/Adafruit_SI5351.cpp |
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# AN619 = https://www.silabs.com/documents/public/application-notes/AN619.pdf |
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25
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=encoding UTF-8 |
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=head1 NAME |
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C - chip driver for F |
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=head1 SYNOPSIS |
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use Device::Chip::Si5351; |
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use Future::AsyncAwait; |
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36
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my $chip = Device::Chip::Si5351->new; |
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await $chip->mount( Device::Chip::Adapter::...->new ); |
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39
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await $chip->init; |
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41
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await $chip->change_pll_config( "A", |
42
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SRC => "XTAL", |
43
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ratio => 24, |
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); |
45
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46
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await $chip->change_multisynth_config( 0, |
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SRC => "PLLA", |
48
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ratio => 50, |
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); |
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51
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await $chip->change_clk_config( 0, |
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SRC => "MSn", |
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PDN => 0, |
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OE => 1, |
55
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); |
56
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57
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await $chip->reset_plls; |
58
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59
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# CLK0 output will now be set to the crystal reference frequency |
60
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# multiplied by 24, divided by 50. Assuming a 25.000MHz reference |
61
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# crystal, the output will therefore be 12.000MHz. |
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63
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=head1 DESCRIPTION |
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65
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This L subclass provides specific communication to a F |
66
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F chip attached to a computer via an I²C adapter. |
67
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68
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The reader is presumed to be familiar with the general operation of this chip; |
69
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the documentation here will not attempt to explain or define chip-specific |
70
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concepts or features, only the use of this module to access them. |
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72
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=cut |
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74
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method I2C_options |
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6
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6
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0
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2519
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{ |
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return ( |
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6
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33
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addr => 0x60, |
78
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max_bitrate => 400E3, |
79
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); |
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} |
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82
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=head1 METHODS |
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84
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=cut |
85
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86
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# Silabs' AN619 gives names for the register fields but not actually the |
87
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# registers themselves. We've made up these names here |
88
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89
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# Many of these registers aren't used in our code (yet). |
90
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use constant { |
91
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# Register numbers are documented in decimal in the AN619 datasheet |
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27022
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REG_STATUS => 0, # (RO) |
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REG_INTFLAGS => 1, |
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REG_INTMASK => 2, |
95
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REG_OEMASK => 3, |
96
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REG_OEBMASK => 9, |
97
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REG_PLLSOURCE => 15, |
98
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99
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# The 8 clock control registers |
100
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REG_CLKCTRL_BASE => 16, |
101
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102
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REG_CLK03DIS => 24, |
103
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REG_CLK47DIS => 25, |
104
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105
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# Multisynth NA+NB have a common structure |
106
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REG_MSNA_BASE => 26, |
107
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REG_MSNB_BASE => 34, |
108
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109
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# Multisynth0 to 5 have a common structure |
110
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REG_MSx_BASE => 42, |
111
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112
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# Multisynth 6 to 7 are special |
113
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REG_MS6_P1L => 90, |
114
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REG_MS7_P1L => 91, |
115
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REG_MS67_DIV => 92, |
116
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117
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# TODO: spread spectrum, VCXO |
118
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119
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# Phase offset - despite its silly name it is a property of the Multisynth |
120
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# unit, not the clock output |
121
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REG_CLKx_PHOFF => 165, |
122
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123
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REG_PLLRST => 177, |
124
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125
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REG_XTAL_CL => 183, |
126
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127
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REG_FANOUT => 187, |
128
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7
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8876
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}; |
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16
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129
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130
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=head2 init |
131
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132
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await $chip->init; |
133
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134
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Performs initialisation setup on the chip as recommended by the datasheet: |
135
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disables all outputs and powers down all output drivers. After this, |
136
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individual outputs can be powered up and enabled again by |
137
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L. |
138
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139
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=cut |
140
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141
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# A copy of the initialise code from the Adafruit driver |
142
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0
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0
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async method init () |
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0
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143
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0
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0
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{ |
144
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# All outputs disabled (bits high) |
145
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0
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0
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await $self->cached_write_reg( REG_OEMASK, "\xFF" ); |
146
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147
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# All output drivers powered down |
148
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await Future->needs_all( |
149
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0
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0
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map { $self->cached_write_reg( REG_CLKCTRL_BASE + $_, "\x80" ) } 0 .. 7 |
150
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); |
151
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0
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0
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1
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0
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} |
152
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153
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=head2 read_status |
154
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155
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$status = await $chip->read_status; |
156
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157
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Reads and returns the chip status register, as a C reference with the |
158
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following keys: |
159
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160
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SYS_INIT => BOOL |
161
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LOL_A => BOOL |
162
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LOL_B => BOOL |
163
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LOS_CLKIN => BOOL |
164
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LOS_XTAL => BOOL |
165
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REVID => INT |
166
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167
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=cut |
168
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169
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bitfield { format => "bytes-LE" }, STATUS => |
170
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SYS_INIT => boolfield( 7 ), |
171
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LOL_A => boolfield( 6 ), |
172
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LOL_B => boolfield( 5 ), |
173
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LOS_CLKIN => boolfield( 4 ), |
174
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LOS_XTAL => boolfield( 3 ), |
175
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REVID => intfield( 0, 2 ), |
176
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; |
177
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178
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1
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1
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async method read_status () |
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1
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2
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179
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1
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3
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{ |
180
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1
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5
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my $bytes = await $self->read_reg( REG_STATUS, 1 ); |
181
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182
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1
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6763
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return { unpack_STATUS( $bytes ) }; |
183
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1
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1
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1
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182
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} |
184
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185
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=head2 read_config |
186
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187
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$config = await $chip->read_config; |
188
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189
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Reads and returns the overall chip configuration, as a C reference with |
190
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the following keys: |
191
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192
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XTAL_CL => "6pF" | "8pF" | "10pF" |
193
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CLKIN_FANOUT => BOOL |
194
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XO_FANOUT => BOOL |
195
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MS_FANOUT => BOOL |
196
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197
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=cut |
198
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199
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# Rather than one giant monster "config" structure, we'll split up |
200
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# chip overall |
201
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# PLLA, PLLB |
202
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# Multisynth0 to Multisynth7 |
203
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# CLK0 to CLK7 outputs |
204
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205
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bitfield { format => "bytes-LE" }, CONFIG => |
206
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# REG_XTAL_CL |
207
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XTAL_CL => enumfield( 6, qw( . 6pF 8pF 10pF ) ), |
208
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# REG_FANOUT |
209
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CLKIN_FANOUT => boolfield( 15 ), |
210
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XO_FANOUT => boolfield( 14 ), |
211
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MS_FANOUT => boolfield( 12 ), |
212
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; |
213
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214
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2
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2
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async method read_config () |
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2
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3
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215
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2
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4
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{ |
216
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2
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8
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my $bytes = join "", |
217
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await $self->cached_read_reg( REG_XTAL_CL, 1 ), |
218
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await $self->cached_read_reg( REG_FANOUT, 1 ); |
219
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220
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2
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8552
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return { unpack_CONFIG( $bytes ) }; |
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1
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274
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} |
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=head2 change_config |
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await $chip->change_config( %changes ); |
226
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Writes changes to the overall chip configuration registers. Any fields not |
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specified will retain their current values. |
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=cut |
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1
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2
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async method change_config ( %changes ) |
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3
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{ |
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1
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2
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my $config = await $self->read_config(); |
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1
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$config->{$_} = $changes{$_} for keys %changes; |
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1
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6
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my ( $xtal_cl, $fanout ) = unpack "(a1)*", pack_CONFIG( %$config ); |
239
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1
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91
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await $self->cached_write_reg( REG_XTAL_CL, $xtal_cl ); |
241
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1
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196
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await $self->cached_write_reg( REG_FANOUT, $fanout ); |
242
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1
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1
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1
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2967
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} |
243
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=head2 read_pll_config |
245
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246
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$config = await $chip->read_pll_config( $pll ) |
247
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Reads and returns the PLL synthesizer configuration registers for the given |
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PLL unit (which should be C<"A"> or C<"B">), as a C reference with the |
250
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following keys: |
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252
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P1 => INT |
253
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P2 => INT |
254
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P3 => INT |
255
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SRC => "XTAL" | "CLKIN" |
256
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257
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Additionally, the following extra fields will be inferred from the basic |
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parameters, as a convenience: |
259
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260
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ratio_a => INT # integral part of ratio |
261
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ratio_b => INT # numerator of fractional part of ratio |
262
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ratio_c => INT # denominator of fractional part of ratio |
263
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264
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ratio => NUM # ratio expressed as a float |
265
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266
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=cut |
267
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268
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sub unpack_PARAMS ( $bytes ) |
269
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17
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17
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0
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25
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{ |
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17
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25
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17
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19
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270
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17
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85
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my ( $p3m, $p3l, $p1h, $p1m, $p1l, $p23h, $p2m, $p2l ) = unpack "(C)8", $bytes; |
271
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17
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32
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$p1h &= 0x03; |
272
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17
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28
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my $p2h = ($p23h)&0x0F; |
273
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17
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25
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my $p3h = ($p23h>>4); |
274
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275
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return ( |
276
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17
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87
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P1 => $p1l | ($p1m << 8) | ($p1h << 16), |
277
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P2 => $p2l | ($p2m << 8) | ($p2h << 16), |
278
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P3 => $p3l | ($p3m << 8) | ($p3h << 16), |
279
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); |
280
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} |
281
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282
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sub pack_PARAMS ( %params ) |
283
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6
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6
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0
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19
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{ |
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6
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14
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6
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7
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284
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6
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18
|
my ( $p1, $p2, $p3 ) = @params{qw( P1 P2 P3 )}; |
285
|
6
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50
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17
|
$p1 == ($p1 & 0x3FFFF) or croak "P1 out of range"; |
286
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6
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50
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24
|
$p2 == ($p2 & 0xFFFFF) or croak "P2 out of range"; |
287
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6
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50
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12
|
$p3 == ($p3 & 0xFFFFF) or croak "P3 out of range"; |
288
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289
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6
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40
|
return pack "C C C C C C C C", |
290
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|
|
($p3>>8)&0xFF, ($p3)&0xFF, ($p1>>16), ($p1>>8)&0xFF, |
291
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|
($p1)&0xFF, ($p3>>16)<<4|($p2>>16), ($p2>>8)&0xFF, ($p2)&0xFF; |
292
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|
} |
293
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294
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|
sub _infer_ratio ( $config ) |
295
|
17
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17
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23
|
{ |
|
17
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24
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17
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21
|
|
296
|
17
|
100
|
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|
43
|
if( $config->{P2} == 0 ) { |
297
|
13
|
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41
|
$config->{ratio_a} = ( $config->{P1} + 512 ) / 128; |
298
|
13
|
|
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|
22
|
$config->{ratio_b} = 0; |
299
|
13
|
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|
17
|
$config->{ratio_c} = 1; |
300
|
|
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|
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} |
301
|
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|
else { |
302
|
4
|
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|
11
|
my $ratio_c = $config->{ratio_c} = $config->{P3}; |
303
|
4
|
|
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|
|
9
|
my $P1_ = $config->{P1} + 512; |
304
|
4
|
|
|
|
|
40
|
$config->{ratio_a} = floor( $P1_ / 128 ); |
305
|
4
|
|
|
|
|
15
|
my $floor = $P1_ - 128 * $config->{ratio_a}; |
306
|
4
|
|
|
|
|
19
|
$config->{ratio_b} = floor( ( $config->{P2} + $floor * $ratio_c ) / 128 ); |
307
|
|
|
|
|
|
|
} |
308
|
|
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|
|
|
|
|
309
|
17
|
|
|
|
|
51
|
$config->{ratio} = $config->{ratio_a} + $config->{ratio_b} / $config->{ratio_c}; |
310
|
|
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|
|
} |
311
|
|
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|
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|
312
|
|
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|
|
|
sub _calc_param ( $config ) |
313
|
5
|
|
|
5
|
|
9
|
{ |
|
5
|
|
|
|
|
7
|
|
|
5
|
|
|
|
|
8
|
|
314
|
|
|
|
|
|
|
# These equations taken straight from AN691 |
315
|
5
|
|
|
|
|
9
|
my ( $ratio_a, $ratio_b, $ratio_c ) = @{$config}{qw( ratio_a ratio_b ratio_c )}; |
|
5
|
|
|
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|
12
|
|
316
|
|
|
|
|
|
|
|
317
|
5
|
|
|
|
|
40
|
my $floor = floor( 128 * $ratio_b / $ratio_c ); |
318
|
5
|
|
|
|
|
19
|
$config->{P1} = 128 * $ratio_a + $floor - 512; |
319
|
5
|
|
|
|
|
14
|
$config->{P2} = 128 * $ratio_b - $ratio_c * $floor; |
320
|
5
|
|
|
|
|
12
|
$config->{P3} = $ratio_c; |
321
|
|
|
|
|
|
|
} |
322
|
|
|
|
|
|
|
|
323
|
5
|
|
|
|
|
10
|
async method read_pll_config ( $pll ) |
|
5
|
|
|
|
|
9
|
|
|
5
|
|
|
|
|
9
|
|
324
|
5
|
|
|
|
|
30
|
{ |
325
|
5
|
0
|
|
|
|
18
|
my $regbase = ( $pll eq "A" ) ? REG_MSNA_BASE : |
|
|
50
|
|
|
|
|
|
326
|
|
|
|
|
|
|
( $pll eq "B" ) ? REG_MSNB_BASE : croak "Invalid PLL choice '$pll'"; |
327
|
|
|
|
|
|
|
|
328
|
5
|
|
|
|
|
26
|
my $bytes = await $self->cached_read_reg( $regbase, 8 ); |
329
|
|
|
|
|
|
|
|
330
|
5
|
|
|
|
|
10134
|
my %config = unpack_PARAMS( $bytes ); |
331
|
|
|
|
|
|
|
|
332
|
5
|
|
|
|
|
19
|
my $pllsrc = unpack "C", await $self->cached_read_reg( REG_PLLSOURCE, 1 ); |
333
|
5
|
50
|
|
|
|
2149
|
$pllsrc &= ( $pll eq "A" ) ? (1<<2) : (1<<3); |
334
|
|
|
|
|
|
|
|
335
|
5
|
|
|
|
|
17
|
$config{SRC} = (qw( XTAL CLKIN ))[ !!$pllsrc ]; |
336
|
|
|
|
|
|
|
|
337
|
5
|
|
|
|
|
20
|
_infer_ratio \%config; |
338
|
|
|
|
|
|
|
|
339
|
5
|
|
|
|
|
38
|
return \%config; |
340
|
5
|
|
|
5
|
1
|
14188
|
} |
341
|
|
|
|
|
|
|
|
342
|
|
|
|
|
|
|
=head2 change_pll_config |
343
|
|
|
|
|
|
|
|
344
|
|
|
|
|
|
|
await $chip->change_pll_config( $pll, %changes ) |
345
|
|
|
|
|
|
|
|
346
|
|
|
|
|
|
|
Writes changes to the PLL synthesizer configuration registers for the given |
347
|
|
|
|
|
|
|
PLL unit. Any fields not specified will retain their current values. |
348
|
|
|
|
|
|
|
|
349
|
|
|
|
|
|
|
As a convenience, the feedback division ratio can be supplied using the three |
350
|
|
|
|
|
|
|
C parameters, rather than the raw C values. |
351
|
|
|
|
|
|
|
|
352
|
|
|
|
|
|
|
To set an integer ratio, this can alternatively be supplied directly by the |
353
|
|
|
|
|
|
|
C parameter. This must be an integer, however. To avoid floating-point |
354
|
|
|
|
|
|
|
inaccuracies in fractional ratios, the three C parameters must be |
355
|
|
|
|
|
|
|
used if the ratio is not a simple integer. |
356
|
|
|
|
|
|
|
|
357
|
|
|
|
|
|
|
=cut |
358
|
|
|
|
|
|
|
|
359
|
2
|
|
|
|
|
4
|
async method change_pll_config ( $pll, %changes ) |
|
2
|
|
|
|
|
5
|
|
|
2
|
|
|
|
|
7
|
|
|
2
|
|
|
|
|
3
|
|
360
|
2
|
|
|
|
|
10
|
{ |
361
|
2
|
0
|
|
|
|
7
|
my $regbase = ( $pll eq "A" ) ? REG_MSNA_BASE : |
|
|
50
|
|
|
|
|
|
362
|
|
|
|
|
|
|
( $pll eq "B" ) ? REG_MSNB_BASE : croak "Invalid PLL choice '$pll'"; |
363
|
|
|
|
|
|
|
|
364
|
2
|
|
|
|
|
9
|
my $config = await $self->read_pll_config( $pll ); |
365
|
|
|
|
|
|
|
|
366
|
2
|
100
|
|
|
|
50
|
if( exists $changes{ratio} ) { |
367
|
1
|
|
|
|
|
3
|
my $ratio = delete $changes{ratio}; |
368
|
|
|
|
|
|
|
|
369
|
1
|
50
|
33
|
|
|
9
|
15 <= $ratio and $ratio < 91 or |
370
|
|
|
|
|
|
|
croak "Cannot set PLL multiplier ratio to $ratio"; |
371
|
1
|
50
|
|
|
|
5
|
$ratio == int $ratio or |
372
|
|
|
|
|
|
|
croak "Cannot use 'ratio' to set a non-integer ratio; please supply ratio_a, ratio_b, ratio_c individually"; |
373
|
|
|
|
|
|
|
|
374
|
1
|
|
|
|
|
3
|
$changes{ratio_a} = $ratio; |
375
|
1
|
|
|
|
|
2
|
$changes{ratio_b} = 0; |
376
|
1
|
|
|
|
|
2
|
$changes{ratio_c} = 1; |
377
|
|
|
|
|
|
|
} |
378
|
|
|
|
|
|
|
|
379
|
2
|
0
|
33
|
|
|
8
|
if( exists $changes{ratio_a} or exists $changes{ratio_b} or exists $changes{ratio_c} ) { |
|
|
|
0
|
|
|
|
|
380
|
2
|
|
|
|
|
6
|
_calc_param( \%changes ); |
381
|
|
|
|
|
|
|
} |
382
|
|
|
|
|
|
|
|
383
|
2
|
|
33
|
|
|
14
|
exists $changes{$_} and $config->{$_} = $changes{$_} for qw( P1 P2 P3 ); |
384
|
|
|
|
|
|
|
|
385
|
2
|
|
|
|
|
11
|
my $bytes = pack_PARAMS( %$config ); |
386
|
|
|
|
|
|
|
|
387
|
2
|
|
|
|
|
21
|
await $self->cached_write_reg( $regbase, $bytes ); |
388
|
|
|
|
|
|
|
|
389
|
2
|
|
|
|
|
7958
|
await $self->reset_plls; |
390
|
2
|
|
|
2
|
1
|
5868
|
} |
391
|
|
|
|
|
|
|
|
392
|
|
|
|
|
|
|
=head2 reset_plls |
393
|
|
|
|
|
|
|
|
394
|
|
|
|
|
|
|
await $chip->reset_plls; |
395
|
|
|
|
|
|
|
|
396
|
|
|
|
|
|
|
Resets the PLLs. This method should be called at the end of configuration to |
397
|
|
|
|
|
|
|
reset the PLL and divider units to begin outputting the configured |
398
|
|
|
|
|
|
|
frequencies. |
399
|
|
|
|
|
|
|
|
400
|
|
|
|
|
|
|
=cut |
401
|
|
|
|
|
|
|
|
402
|
2
|
|
|
|
|
4
|
async method reset_plls () |
|
2
|
|
|
|
|
4
|
|
403
|
2
|
|
|
|
|
9
|
{ |
404
|
|
|
|
|
|
|
# This magic value 0xAC doesn't appear in the data sheet itself, but most |
405
|
|
|
|
|
|
|
# of the other drivers use it anyway and it seems to work. |
406
|
2
|
|
|
|
|
6
|
await $self->write_reg( REG_PLLRST, pack "C", 0xAC ); |
407
|
2
|
|
|
2
|
1
|
4
|
} |
408
|
|
|
|
|
|
|
|
409
|
|
|
|
|
|
|
=head2 read_multisynth_config |
410
|
|
|
|
|
|
|
|
411
|
|
|
|
|
|
|
$config = await $chip->read_multisynth_config( $idx ) |
412
|
|
|
|
|
|
|
|
413
|
|
|
|
|
|
|
Reads and returns the Multisynth frequency divider configuration registers for |
414
|
|
|
|
|
|
|
the given unit (which should be an integer C<0> to C<5>), as a C |
415
|
|
|
|
|
|
|
reference with the following keys: |
416
|
|
|
|
|
|
|
|
417
|
|
|
|
|
|
|
P1 => INT |
418
|
|
|
|
|
|
|
P2 => INT |
419
|
|
|
|
|
|
|
P3 => INT |
420
|
|
|
|
|
|
|
DIVBY4 => BOOL |
421
|
|
|
|
|
|
|
INT => BOOL |
422
|
|
|
|
|
|
|
SRC => "PLLA" | "PLLB" |
423
|
|
|
|
|
|
|
PHOFF => INT |
424
|
|
|
|
|
|
|
|
425
|
|
|
|
|
|
|
Note that this method returns the setting of the appropriate phase-offset |
426
|
|
|
|
|
|
|
register. Even though the datasheet names this as if it were related to the |
427
|
|
|
|
|
|
|
clock output unit, it in fact relates to the Multisynth divider. |
428
|
|
|
|
|
|
|
|
429
|
|
|
|
|
|
|
Additionally, the following extra fields will be inferred from the basic |
430
|
|
|
|
|
|
|
parameters, as a convenience: |
431
|
|
|
|
|
|
|
|
432
|
|
|
|
|
|
|
ratio_a => INT # integral part of ratio |
433
|
|
|
|
|
|
|
ratio_b => INT # numerator of fractional part of ratio |
434
|
|
|
|
|
|
|
ratio_c => INT # denominator of fractional part of ratio |
435
|
|
|
|
|
|
|
|
436
|
|
|
|
|
|
|
ratio => NUM # ratio expressed as a float |
437
|
|
|
|
|
|
|
|
438
|
|
|
|
|
|
|
Note that the integer-only Multisynth units 6 and 7 are not currently |
439
|
|
|
|
|
|
|
supported. |
440
|
|
|
|
|
|
|
|
441
|
|
|
|
|
|
|
=cut |
442
|
|
|
|
|
|
|
|
443
|
|
|
|
|
|
|
bitfield { format => "bytes-LE" }, MS_CLKCTRL => |
444
|
|
|
|
|
|
|
# REG_CLKnCTRL |
445
|
|
|
|
|
|
|
INT => boolfield( 6 ), |
446
|
|
|
|
|
|
|
SRC => enumfield( 5, qw( PLLA PLLB ) ), |
447
|
|
|
|
|
|
|
; |
448
|
|
|
|
|
|
|
|
449
|
12
|
|
|
|
|
14
|
async method read_multisynth_config ( $idx ) |
|
12
|
|
|
|
|
15
|
|
|
12
|
|
|
|
|
13
|
|
450
|
12
|
|
|
|
|
25
|
{ |
451
|
|
|
|
|
|
|
# TODO: multisynths 6 and 7 are integer-only and different layout |
452
|
|
|
|
|
|
|
|
453
|
12
|
50
|
33
|
|
|
42
|
$idx >= 0 and $idx <= 5 or croak "Invalid Multisynth choice '$idx'"; |
454
|
12
|
|
|
|
|
23
|
my $regbase = REG_MSx_BASE + 8*$idx; |
455
|
|
|
|
|
|
|
|
456
|
12
|
|
|
|
|
31
|
my $parambytes = await $self->cached_read_reg( $regbase, 8 ); |
457
|
12
|
|
|
|
|
18049
|
my $clkctrlbyte = await $self->cached_read_reg( REG_CLKCTRL_BASE + $idx, 1 ); |
458
|
|
|
|
|
|
|
|
459
|
12
|
|
|
|
|
4991
|
my %config = ( |
460
|
|
|
|
|
|
|
unpack_PARAMS( $parambytes ), |
461
|
|
|
|
|
|
|
unpack_MS_CLKCTRL( $clkctrlbyte ), |
462
|
|
|
|
|
|
|
); |
463
|
|
|
|
|
|
|
|
464
|
12
|
|
|
|
|
345
|
my $divby4 = ( ( unpack "x x C", $parambytes ) >> 2 ) & 0x03; |
465
|
12
|
|
|
|
|
27
|
$config{DIVBY4} = !!$divby4; |
466
|
|
|
|
|
|
|
|
467
|
12
|
|
|
|
|
26
|
$config{PHOFF} = unpack "C", await $self->cached_read_reg( REG_CLKx_PHOFF, 1 ); |
468
|
|
|
|
|
|
|
|
469
|
12
|
|
|
|
|
3728
|
_infer_ratio \%config; |
470
|
|
|
|
|
|
|
|
471
|
12
|
|
|
|
|
50
|
return \%config; |
472
|
12
|
|
|
12
|
1
|
5314
|
} |
473
|
|
|
|
|
|
|
|
474
|
|
|
|
|
|
|
=head2 change_multisynth_config |
475
|
|
|
|
|
|
|
|
476
|
|
|
|
|
|
|
await $chip->change_multisynth_config( $pll, %changes ) |
477
|
|
|
|
|
|
|
|
478
|
|
|
|
|
|
|
Writes changes to the Multisynth frequency divider configuration registers |
479
|
|
|
|
|
|
|
for the given unit. Any fields not specified will retain their current values. |
480
|
|
|
|
|
|
|
|
481
|
|
|
|
|
|
|
As a convenience, the division ratio can be supplied using the three |
482
|
|
|
|
|
|
|
C parameters, rather than the raw C values. |
483
|
|
|
|
|
|
|
|
484
|
|
|
|
|
|
|
To set an integer ratio, this can alternatively be supplied directly by the |
485
|
|
|
|
|
|
|
C parameter. This must be an integer, however. To avoid floating-point |
486
|
|
|
|
|
|
|
inaccuracies in fractional ratios, the three C parameters must be |
487
|
|
|
|
|
|
|
used if the ratio is not a simple integer. |
488
|
|
|
|
|
|
|
|
489
|
|
|
|
|
|
|
=cut |
490
|
|
|
|
|
|
|
|
491
|
4
|
|
|
|
|
4
|
async method change_multisynth_config ( $idx, %changes ) |
|
4
|
|
|
|
|
6
|
|
|
4
|
|
|
|
|
10
|
|
|
4
|
|
|
|
|
4
|
|
492
|
4
|
|
|
|
|
9
|
{ |
493
|
|
|
|
|
|
|
# TODO: multisynths 6 and 7 are integer-only and different layout |
494
|
|
|
|
|
|
|
|
495
|
4
|
50
|
33
|
|
|
19
|
$idx >= 0 and $idx <= 5 or croak "Invalid Multisynth choice '$idx'"; |
496
|
4
|
|
|
|
|
9
|
my $regbase = REG_MSx_BASE + 8*$idx; |
497
|
|
|
|
|
|
|
|
498
|
4
|
|
|
|
|
9
|
my $config = await $self->read_multisynth_config( $idx ); |
499
|
|
|
|
|
|
|
|
500
|
4
|
100
|
|
|
|
119
|
if( exists $changes{ratio} ) { |
501
|
1
|
|
|
|
|
2
|
my $ratio = delete $changes{ratio}; |
502
|
|
|
|
|
|
|
|
503
|
1
|
50
|
33
|
|
|
5
|
8 <= $ratio and $ratio <= 900 or |
504
|
|
|
|
|
|
|
croak "Cannot set Multisynth divider ratio to $ratio"; |
505
|
1
|
50
|
|
|
|
2
|
$ratio == int $ratio or |
506
|
|
|
|
|
|
|
croak "Cannot use 'ratio' to set a non-integer ratio; please supply ratio_a, ratio_b, ratio_c individually"; |
507
|
|
|
|
|
|
|
|
508
|
1
|
|
|
|
|
2
|
$changes{ratio_a} = $ratio; |
509
|
1
|
|
|
|
|
1
|
$changes{ratio_b} = 0; |
510
|
1
|
|
|
|
|
2
|
$changes{ratio_c} = 1; |
511
|
|
|
|
|
|
|
} |
512
|
|
|
|
|
|
|
|
513
|
4
|
50
|
66
|
|
|
14
|
if( exists $changes{ratio_a} or exists $changes{ratio_b} or exists $changes{ratio_c} ) { |
|
|
|
33
|
|
|
|
|
514
|
3
|
|
|
|
|
9
|
_calc_param( \%changes ); |
515
|
|
|
|
|
|
|
} |
516
|
|
|
|
|
|
|
|
517
|
4
|
|
66
|
|
|
27
|
exists $changes{$_} and $config->{$_} = $changes{$_} for qw( P1 P2 P3 INT SRC ); |
518
|
|
|
|
|
|
|
|
519
|
4
|
|
|
|
|
7
|
my $paramsbytes = pack_PARAMS( %{$config}{qw( P1 P2 P3 )} ); |
|
4
|
|
|
|
|
10
|
|
520
|
4
|
|
|
|
|
8
|
my $clkctrlbyte = pack_MS_CLKCTRL( %{$config}{qw( INT SRC )} ); |
|
4
|
|
|
|
|
12
|
|
521
|
4
|
|
|
|
|
195
|
my $phoff = delete $config->{PHOFF}; |
522
|
4
|
50
|
33
|
|
|
24
|
$phoff >= 0 and $phoff < 128 or |
523
|
|
|
|
|
|
|
croak "Invalid PHOFF setting"; |
524
|
|
|
|
|
|
|
|
525
|
4
|
|
|
|
|
29
|
await $self->cached_write_reg_masked( $regbase, $paramsbytes, "\xFF\xFF\x03\xFF\xFF\xFF\xFF\xFF" ); |
526
|
4
|
|
|
|
|
5059
|
await $self->cached_write_reg_masked( REG_CLKCTRL_BASE + $idx, $clkctrlbyte, "\x60" ); |
527
|
4
|
|
|
|
|
2377
|
await $self->cached_write_reg ( REG_CLKx_PHOFF, pack "C", $phoff ); |
528
|
4
|
|
|
4
|
1
|
10856
|
} |
529
|
|
|
|
|
|
|
|
530
|
|
|
|
|
|
|
=head2 read_clk_config |
531
|
|
|
|
|
|
|
|
532
|
|
|
|
|
|
|
$config = $chip->read_clk_config( $idx ) |
533
|
|
|
|
|
|
|
|
534
|
|
|
|
|
|
|
Reads and returns the clock output pin configuration registers for the given |
535
|
|
|
|
|
|
|
pin index (in the range 0 to 5), as a C reference with the following |
536
|
|
|
|
|
|
|
keys: |
537
|
|
|
|
|
|
|
|
538
|
|
|
|
|
|
|
IDRV => "2mA" | "4mA" | "6mA" | "8mA" |
539
|
|
|
|
|
|
|
SRC => "XTAL" | "CLKIN" | "MS04" | "MSn" |
540
|
|
|
|
|
|
|
INV => BOOL |
541
|
|
|
|
|
|
|
PDN => BOOL |
542
|
|
|
|
|
|
|
DIV => 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 |
543
|
|
|
|
|
|
|
OE => BOOL |
544
|
|
|
|
|
|
|
|
545
|
|
|
|
|
|
|
Note that the C field has positive logic; it is true when the output is |
546
|
|
|
|
|
|
|
enabled (by the C register having a 0 bit in the corresponding |
547
|
|
|
|
|
|
|
position). |
548
|
|
|
|
|
|
|
|
549
|
|
|
|
|
|
|
=cut |
550
|
|
|
|
|
|
|
|
551
|
|
|
|
|
|
|
bitfield { format => "bytes-LE" }, CLKCTRL => |
552
|
|
|
|
|
|
|
# REG_CLKnCTRL |
553
|
|
|
|
|
|
|
IDRV => enumfield( 0, qw( 2mA 4mA 6mA 8mA ) ), |
554
|
|
|
|
|
|
|
SRC => enumfield( 2, qw( XTAL CLKIN MS04 MSn ) ), |
555
|
|
|
|
|
|
|
INV => boolfield( 4 ), |
556
|
|
|
|
|
|
|
PDN => boolfield( 7 ), |
557
|
|
|
|
|
|
|
# REG_MSnBASE+2 |
558
|
|
|
|
|
|
|
DIV => enumfield( 12, qw( 1 2 4 8 16 32 64 128 ) ), |
559
|
|
|
|
|
|
|
; |
560
|
|
|
|
|
|
|
|
561
|
9
|
|
|
|
|
21
|
async method read_clk_config ( $idx ) |
|
9
|
|
|
|
|
12
|
|
|
9
|
|
|
|
|
11
|
|
562
|
9
|
|
|
|
|
24
|
{ |
563
|
9
|
50
|
33
|
|
|
39
|
$idx >= 0 and $idx <= 7 or croak "Invalid Clk choice '$idx'"; |
564
|
|
|
|
|
|
|
|
565
|
9
|
|
|
|
|
35
|
my $bytes = join "", |
566
|
|
|
|
|
|
|
await $self->cached_read_reg( REG_CLKCTRL_BASE + $idx, 1 ), |
567
|
|
|
|
|
|
|
await $self->cached_read_reg( REG_MSx_BASE + 8*$idx + 2, 1 ); |
568
|
|
|
|
|
|
|
|
569
|
9
|
|
|
|
|
12257
|
my %config = unpack_CLKCTRL( $bytes ); |
570
|
|
|
|
|
|
|
|
571
|
9
|
|
|
|
|
503
|
my $oemask = unpack "C", await $self->cached_read_reg( REG_OEMASK, 1 ); |
572
|
9
|
|
|
|
|
3716
|
$config{OE} = !( $oemask & (1<<$idx) ); |
573
|
|
|
|
|
|
|
|
574
|
9
|
|
|
|
|
41
|
return \%config; |
575
|
9
|
|
|
9
|
1
|
2861
|
} |
576
|
|
|
|
|
|
|
|
577
|
|
|
|
|
|
|
=head2 change_clk_config |
578
|
|
|
|
|
|
|
|
579
|
|
|
|
|
|
|
await $chip->change_clk_config( $idx, %changes ); |
580
|
|
|
|
|
|
|
|
581
|
|
|
|
|
|
|
Writes changes to the clock output pin configuration registers for the given |
582
|
|
|
|
|
|
|
pin index. Any fields not specified will retain their current values. |
583
|
|
|
|
|
|
|
|
584
|
|
|
|
|
|
|
=cut |
585
|
|
|
|
|
|
|
|
586
|
3
|
|
|
|
|
4
|
async method change_clk_config ( $idx, %changes ) |
|
3
|
|
|
|
|
6
|
|
|
3
|
|
|
|
|
7
|
|
|
3
|
|
|
|
|
5
|
|
587
|
3
|
|
|
|
|
10
|
{ |
588
|
3
|
50
|
33
|
|
|
18
|
$idx >= 0 and $idx <= 7 or croak "Invalid Clk choice '$idx'"; |
589
|
|
|
|
|
|
|
|
590
|
3
|
|
|
|
|
9
|
my $config = await $self->read_clk_config( $idx ); |
591
|
|
|
|
|
|
|
|
592
|
3
|
|
|
|
|
75
|
$config->{$_} = $changes{$_} for keys %changes; |
593
|
|
|
|
|
|
|
|
594
|
|
|
|
|
|
|
# OE is inverted sense |
595
|
3
|
50
|
|
|
|
11
|
my $oemask = delete $config->{OE} ? "\x00" : "\xFF"; |
596
|
3
|
|
|
|
|
15
|
my ( $clkctrl, $ms ) = unpack "(a1)*", pack_CLKCTRL( %$config ); |
597
|
|
|
|
|
|
|
|
598
|
3
|
|
|
|
|
301
|
await $self->cached_write_reg_masked( REG_CLKCTRL_BASE + $idx, $clkctrl, "\x9F" ); |
599
|
3
|
|
|
|
|
2134
|
await $self->cached_write_reg_masked( REG_MSx_BASE + 8*$idx + 2, $ms, "\xFC" ); |
600
|
|
|
|
|
|
|
|
601
|
3
|
|
|
|
|
4158
|
await $self->cached_write_reg_masked( REG_OEMASK, $oemask, pack "C", (1<<$idx) ); |
602
|
3
|
|
|
3
|
1
|
7816
|
} |
603
|
|
|
|
|
|
|
|
604
|
|
|
|
|
|
|
=head1 TODO |
605
|
|
|
|
|
|
|
|
606
|
|
|
|
|
|
|
This module is missing support for several chip features, mostly because I |
607
|
|
|
|
|
|
|
only have the MSOP-10 version of the F chip, so I cannot actually |
608
|
|
|
|
|
|
|
test: |
609
|
|
|
|
|
|
|
|
610
|
|
|
|
|
|
|
=over 4 |
611
|
|
|
|
|
|
|
|
612
|
|
|
|
|
|
|
=item * |
613
|
|
|
|
|
|
|
|
614
|
|
|
|
|
|
|
Integer-only multisynth units 6 and 7 and their associated clock output pins. |
615
|
|
|
|
|
|
|
|
616
|
|
|
|
|
|
|
=item * |
617
|
|
|
|
|
|
|
|
618
|
|
|
|
|
|
|
The VCXO of F. |
619
|
|
|
|
|
|
|
|
620
|
|
|
|
|
|
|
=item * |
621
|
|
|
|
|
|
|
|
622
|
|
|
|
|
|
|
The CLKIN of F. |
623
|
|
|
|
|
|
|
|
624
|
|
|
|
|
|
|
=back |
625
|
|
|
|
|
|
|
|
626
|
|
|
|
|
|
|
Additionally, lacking a spectrum analyser I cannot confirm operation of: |
627
|
|
|
|
|
|
|
|
628
|
|
|
|
|
|
|
=over 4 |
629
|
|
|
|
|
|
|
|
630
|
|
|
|
|
|
|
=item * |
631
|
|
|
|
|
|
|
|
632
|
|
|
|
|
|
|
Spread-spectrum parameters of PLLA. |
633
|
|
|
|
|
|
|
|
634
|
|
|
|
|
|
|
=back |
635
|
|
|
|
|
|
|
|
636
|
|
|
|
|
|
|
=head1 AUTHOR |
637
|
|
|
|
|
|
|
|
638
|
|
|
|
|
|
|
Paul Evans |
639
|
|
|
|
|
|
|
|
640
|
|
|
|
|
|
|
=cut |
641
|
|
|
|
|
|
|
|
642
|
|
|
|
|
|
|
0x55AA; |