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# You may distribute under the terms of either the GNU General Public License |
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# or the Artistic License (the same terms as Perl itself) |
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# |
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# (C) Paul Evans, 2015-2021 -- leonerd@leonerd.org.uk |
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833
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use v5.26; |
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562
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use Object::Pad 0.57; |
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10083
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package Device::Chip::MCP23x17 0.05; |
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class Device::Chip::MCP23x17 |
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:isa(Device::Chip); |
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16473
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1432
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use Future::AsyncAwait; |
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=head1 NAME |
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C - chip driver for the F family |
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=head1 SYNOPSIS |
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use Device::Chip::MCP23S17; |
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use Future::AsyncAwait; |
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use constant { HIGH => 0xFFFF, LOW => 0 }; |
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26
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my $chip = Device::Chip::MCP23S17->new; |
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await $chip->mount( Device::Chip::Adapter::...->new ); |
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29
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foreach my $bit ( 0 .. 15 ) { |
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await $chip->write_gpio( HIGH, 1 << $bit ); |
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sleep 1; |
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await $chip->write_gpio( LOW, 1 << $bit ); |
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} |
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=head1 DESCRIPTION |
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This L subclass provides specific communication to the |
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F F family of chips. |
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40
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This module itself is an abstract base; to talk to a specific chip see |
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one of the following subclasses: |
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43
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=over 4 |
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45
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F over SPI - see L |
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47
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=back |
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48
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49
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Aside from the method of communication with the actual chip hardware, these |
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modules all provide the same higher-level API to the containing application. |
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52
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This module currently only supports a chip running in the C |
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53
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configuration. |
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54
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55
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=cut |
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56
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57
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ADJUST |
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58
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{ |
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59
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$self->reset; |
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60
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} |
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61
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62
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=head1 MOUNT PARAMETERS |
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63
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64
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=head2 reset |
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65
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66
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The name of the GPIO line on the adapter that is connected to the C |
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67
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pin of the chip, if there is one. This will be used by the L method. |
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68
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69
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=cut |
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70
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71
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has $_resetpin; |
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72
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73
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5
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11
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async method mount ( $adapter, %params ) |
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5
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10
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5
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8
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5
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9
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74
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5
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15
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{ |
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75
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5
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12
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$_resetpin = delete $params{reset}; |
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76
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77
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5
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37
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return await $self->SUPER::mount( $adapter, %params ); |
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78
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5
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5
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1
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550
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} |
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79
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80
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use constant { |
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81
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# Register allocations when in IOCON.BANK=0 mode |
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82
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# TODO: we don't yet support BANK=1 mode |
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83
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6
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7858
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REG_IODIR => 0x00, |
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84
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REG_IPOL => 0x02, |
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85
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REG_GPINTEN => 0x04, |
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86
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REG_DEFVAL => 0x06, |
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87
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REG_INTCON => 0x08, |
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88
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REG_IOCON => 0x0A, |
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89
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REG_GPPU => 0x0C, |
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90
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REG_INTF => 0x0E, |
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91
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REG_INTCAP => 0x10, |
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92
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REG_GPIO => 0x12, |
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93
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REG_OLAT => 0x14, |
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94
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6
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6
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1602
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}; |
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6
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13
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95
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96
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has %_regcache; |
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97
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98
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17
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24
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async method _cached_maskedwrite_u16 ( $name, $val, $mask ) |
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17
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23
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17
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23
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17
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21
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17
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21
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99
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17
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40
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{ |
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100
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17
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44
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my $want = ( $_regcache{$name} & ~$mask ) | ( $val & $mask ); |
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101
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102
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17
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100
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81
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return if ( my $got = $_regcache{$name} ) == $want; |
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103
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11
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22
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$_regcache{$name} = $want; |
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104
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105
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11
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86
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my $reg = __PACKAGE__->can( "REG_\U$name" )->(); |
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106
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107
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11
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100
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49
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if( ( $got & 0xFF00 ) == ( $want & 0xFF00 ) ) { |
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50
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108
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# low-byte write |
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109
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9
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59
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await $self->write_reg( $reg, pack "C", $want & 0x00FF ); |
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110
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} |
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111
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elsif( ( $got & 0x00FF ) == ( $want & 0x00FF ) ) { |
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112
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2
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11
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await $self->write_reg( $reg+1, pack "C", ( $want & 0xFF00 ) >> 8 ); |
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113
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} |
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114
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else { |
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115
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0
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0
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await $self->write_reg( $reg, pack "S<", $want ); |
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116
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} |
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117
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17
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17
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10004
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} |
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118
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119
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=head1 METHODS |
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120
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121
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The following methods documented in an C expression return L |
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122
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instances. |
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123
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124
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Each method that takes a C<$mask> parameter uses it to select which IO pins |
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125
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are affected. The mask is a 16-bit integer; selecting only those pins for |
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126
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which bits are set. The lower 8 bits relate to the C pins, the higher 8 |
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127
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to the C pins. Pins that are not selected by the mask remain unaffected. |
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128
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129
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=cut |
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130
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131
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=head2 reset |
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132
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133
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await $chip->reset; |
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134
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135
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Resets the cached register values back to their power-up defaults. |
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136
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137
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Additionally, if the C mount parameter is defined, pulses the C |
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138
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pin of the chip. |
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139
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140
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=cut |
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141
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142
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async method reset |
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143
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5
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13
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{ |
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144
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# Default registers |
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145
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5
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15
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$_regcache{iodir} = 0xffff; |
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146
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5
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11
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$_regcache{olat} = 0x0000; |
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147
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5
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11
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$_regcache{ipol} = 0x0000; |
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148
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5
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11
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$_regcache{gppu} = 0x0000; |
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149
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150
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5
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50
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91
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if( defined( my $reset = $_resetpin ) ) { |
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151
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0
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0
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await $self->protocol->write_gpios( { $reset => 0 } ); |
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152
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0
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0
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await $self->protocol->write_gpios( { $reset => 1 } ); |
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153
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} |
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154
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5
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5
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1
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13
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} |
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155
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156
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=head2 write_gpio |
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157
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158
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await $chip->write_gpio( $val, $mask ); |
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159
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160
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Sets the pins named in the C<$mask> to be outputs, and sets their values from |
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161
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the bits in C<$val>. Both values are 16-bit integers. |
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162
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163
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=cut |
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164
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165
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6
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11
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async method write_gpio ( $val, $mask ) |
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6
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10
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6
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8
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6
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9
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166
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6
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18
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{ |
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167
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# Write the values before the direction, so as not to cause glitches |
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168
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6
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33
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await $self->_cached_maskedwrite_u16( olat => $val, $mask ), |
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169
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await $self->_cached_maskedwrite_u16( iodir => 0x0000, $mask ), |
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170
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6
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6
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1
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19508
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} |
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171
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172
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=head2 read_gpio |
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173
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174
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$val = await $chip->read_gpio( $mask ); |
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175
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176
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Sets the pins named in the C<$mask> to be inputs, and reads the current pin |
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177
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values of them. The mask and the return value are 16-bit integers. |
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178
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179
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=cut |
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180
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181
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2
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2
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async method read_gpio ( $mask ) |
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2
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48
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2
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5
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182
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2
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6
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{ |
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183
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2
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13
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await $self->tris_gpio( $mask ); |
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184
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185
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2
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1279
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my $val = unpack "S<", await $self->read_reg( REG_GPIO, 2 ); |
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186
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2
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111
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return $val & $mask; |
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187
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2
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2
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1
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268
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} |
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188
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189
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=head2 tris_gpio |
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190
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191
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await $chip->tris_gpio( $mask ); |
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192
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193
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Sets the pins named in the C<$mask> to be inputs ("tristate"). The mask is a |
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194
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16-bit integer. |
|
195
|
|
|
|
|
|
|
|
|
196
|
|
|
|
|
|
|
=cut |
|
197
|
|
|
|
|
|
|
|
|
198
|
3
|
|
|
|
|
4
|
async method tris_gpio ( $mask ) |
|
|
3
|
|
|
|
|
5
|
|
|
|
3
|
|
|
|
|
5
|
|
|
199
|
3
|
|
|
|
|
8
|
{ |
|
200
|
3
|
|
|
|
|
10
|
await $self->_cached_maskedwrite_u16( iodir => 0xFFFF, $mask ); |
|
201
|
3
|
|
|
3
|
1
|
1269
|
} |
|
202
|
|
|
|
|
|
|
|
|
203
|
|
|
|
|
|
|
=head2 set_input_polarity |
|
204
|
|
|
|
|
|
|
|
|
205
|
|
|
|
|
|
|
await $chip->set_input_polarity( $pol, $mask ); |
|
206
|
|
|
|
|
|
|
|
|
207
|
|
|
|
|
|
|
Sets the input polarity of the pins given by C<$mask> to be the values given |
|
208
|
|
|
|
|
|
|
in C<$pol>. Pins associated with bits set in C<$pol> will read with an |
|
209
|
|
|
|
|
|
|
inverted sense. Both values are 16-bit integers. |
|
210
|
|
|
|
|
|
|
|
|
211
|
|
|
|
|
|
|
=cut |
|
212
|
|
|
|
|
|
|
|
|
213
|
1
|
|
|
|
|
2
|
async method set_input_polarity ( $pol, $mask ) |
|
|
1
|
|
|
|
|
2
|
|
|
|
1
|
|
|
|
|
2
|
|
|
|
1
|
|
|
|
|
1
|
|
|
214
|
1
|
|
|
|
|
3
|
{ |
|
215
|
1
|
|
|
|
|
6
|
await $self->_cached_maskedwrite_u16( ipol => $pol, $mask ); |
|
216
|
1
|
|
|
1
|
1
|
277
|
} |
|
217
|
|
|
|
|
|
|
|
|
218
|
|
|
|
|
|
|
=head2 set_input_pullup |
|
219
|
|
|
|
|
|
|
|
|
220
|
|
|
|
|
|
|
await $chip->set_input_pullup( $pullup, $mask ); |
|
221
|
|
|
|
|
|
|
|
|
222
|
|
|
|
|
|
|
Enables or disables the input pullup resistors on the pins given by C<$mask> |
|
223
|
|
|
|
|
|
|
as per the values given by C<$pullup>. Both values are 16-bit integers. |
|
224
|
|
|
|
|
|
|
|
|
225
|
|
|
|
|
|
|
=cut |
|
226
|
|
|
|
|
|
|
|
|
227
|
1
|
|
|
|
|
2
|
async method set_input_pullup ( $pullup, $mask ) |
|
|
1
|
|
|
|
|
2
|
|
|
|
1
|
|
|
|
|
2
|
|
|
|
1
|
|
|
|
|
1
|
|
|
228
|
1
|
|
|
|
|
3
|
{ |
|
229
|
1
|
|
|
|
|
3
|
await $self->_cached_maskedwrite_u16( gppu => $pullup, $mask ); |
|
230
|
1
|
|
|
1
|
1
|
10653
|
} |
|
231
|
|
|
|
|
|
|
|
|
232
|
|
|
|
|
|
|
=head2 as_adapter |
|
233
|
|
|
|
|
|
|
|
|
234
|
|
|
|
|
|
|
$adapter = $chip->as_adapter; |
|
235
|
|
|
|
|
|
|
|
|
236
|
|
|
|
|
|
|
Returns an instance implementing the L interface, |
|
237
|
|
|
|
|
|
|
allowing access to the GPIO pins via the standard adapter API. See also |
|
238
|
|
|
|
|
|
|
L. |
|
239
|
|
|
|
|
|
|
|
|
240
|
|
|
|
|
|
|
=cut |
|
241
|
|
|
|
|
|
|
|
|
242
|
|
|
|
|
|
|
method as_adapter |
|
243
|
1
|
|
|
1
|
1
|
217
|
{ |
|
244
|
1
|
|
|
|
|
382
|
require Device::Chip::MCP23x17::Adapter; |
|
245
|
1
|
|
|
|
|
9
|
return Device::Chip::MCP23x17::Adapter->new( chip => $self ); |
|
246
|
|
|
|
|
|
|
} |
|
247
|
|
|
|
|
|
|
|
|
248
|
|
|
|
|
|
|
=head1 TODO |
|
249
|
|
|
|
|
|
|
|
|
250
|
|
|
|
|
|
|
=over 4 |
|
251
|
|
|
|
|
|
|
|
|
252
|
|
|
|
|
|
|
=item * |
|
253
|
|
|
|
|
|
|
|
|
254
|
|
|
|
|
|
|
Wrap the interrupt-related registers - C, C, C, |
|
255
|
|
|
|
|
|
|
C, C. Support the interrupt-related bits in C - |
|
256
|
|
|
|
|
|
|
C, C, C. |
|
257
|
|
|
|
|
|
|
|
|
258
|
|
|
|
|
|
|
=item * |
|
259
|
|
|
|
|
|
|
|
|
260
|
|
|
|
|
|
|
Support the general configuration bits in the C register - C, |
|
261
|
|
|
|
|
|
|
C. |
|
262
|
|
|
|
|
|
|
|
|
263
|
|
|
|
|
|
|
=item * |
|
264
|
|
|
|
|
|
|
|
|
265
|
|
|
|
|
|
|
Consider how easy/hard or indeed how useful it might be to support |
|
266
|
|
|
|
|
|
|
C configuration. |
|
267
|
|
|
|
|
|
|
|
|
268
|
|
|
|
|
|
|
=back |
|
269
|
|
|
|
|
|
|
|
|
270
|
|
|
|
|
|
|
=head1 AUTHOR |
|
271
|
|
|
|
|
|
|
|
|
272
|
|
|
|
|
|
|
Paul Evans |
|
273
|
|
|
|
|
|
|
|
|
274
|
|
|
|
|
|
|
=cut |
|
275
|
|
|
|
|
|
|
|
|
276
|
|
|
|
|
|
|
0x55AA; |