blib/lib/Verilog/VCD/Writer/Signal.pm | |||
---|---|---|---|
Criterion | Covered | Total | % |
statement | 30 | 30 | 100.0 |
branch | 6 | 6 | 100.0 |
condition | 4 | 6 | 66.6 |
subroutine | 10 | 10 | 100.0 |
pod | 0 | 1 | 0.0 |
total | 50 | 53 | 94.3 |
line | stmt | bran | cond | sub | pod | time | code |
---|---|---|---|---|---|---|---|
1 | |||||||
2 | |||||||
3 | 4 | 4 | 75181 | perltidy |
|||
4 | 15 | ||||||
4 | 110 | ||||||
4 | 4 | 4 | 17 | |
|||
4 | 7 | ||||||
4 | 73 |