File Coverage

blib/lib/Verilog/Netlist/ModPort.pm

Criterion	Covered	Total	%
statement	53	92	57.6
branch	2	6	33.3
condition	5	10	50.0
subroutine	13	27	48.1
pod	13	21	61.9
total	86	156	55.1

# Verilog - Verilog Perl Modport
# See copyright, etc in below POD section.
######################################################################

package Verilog::Netlist::ModPort;

use Verilog::Netlist;
use Verilog::Netlist::Net;
use Verilog::Netlist::Subclass;
use vars qw($VERSION @ISA);
use strict;
@ISA = qw(Verilog::Netlist::ModPort::Struct
	Verilog::Netlist::Subclass);

$VERSION = '3.478';

structs('new',
	'Verilog::Netlist::ModPort::Struct'
	=>[name     	=> '$', #'	# Name of the module
	   filename 	=> '$', #'	# Filename this came from
	   lineno	=> '$', #'	# Linenumber this came from
	   module	=> '$', #'	# Interface is a member of
	   userdata	=> '%',		# User information
	   attributes	=> '%', #'	# Misc attributes for systemperl or other processors
	   #
	   comment	=> '$', #'	# Comment provided by user
	   _ports	=> '%',		# hash of Verilog::Netlist::Ports
	   _portsordered=> '@',		# list of Verilog::Netlist::Ports as ordered in list of ports
	   _nets	=> '%',		# hash of Verilog::Netlist::Nets
	   ]);

sub delete {
    my $self = shift;
    foreach my $oref ($self->nets) {
	$oref->delete;
    }
    foreach my $oref ($self->ports) {
	$oref->delete;
    }
    my $h = $self->module->{_modports};
    delete $h->{$self->name};
    return undef;
}

######################################################################

sub netlist { return $_[0]->module->netlist; }

sub is_top {}  # Ignored, for module compatibility

sub keyword { return 'modport'; }

sub logger {
    return $_[0]->netlist->logger;
}

sub find_net {
    my $self = shift;
    my $search = shift;
    my $rtn = $self->_nets->{$search}||"";
    #print "FINDNET ",$self->name, " SS $search  $rtn\n";
    return $self->_nets->{$search} || $self->_nets->{"\\".$search." "};
}
sub find_port {
    my $self = shift;
    my $search = shift;
    return $self->_ports->{$search} || $self->_ports->{"\\".$search." "};
}
sub find_port_by_index {
    my $self = shift;
    my $myindex = shift;
    # @{$self->_portsordered}[$myindex-1] returns the name of
    # the port in the module at this index.  Then, this is
    # used to find the port reference via the port hash
    return $self->_ports->{@{$self->_portsordered}[$myindex-1]};
}

sub attrs_sorted {
    return (sort {$a cmp $b} @{$_[0]->attrs});
}
sub nets {
    return (values %{$_[0]->_nets});
}
sub nets_sorted {
    return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_nets}));
}
sub ports {
    return (values %{$_[0]->_ports});
}
sub ports_sorted {
    return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_ports}));
}
sub ports_ordered {
    my $self = shift;
    return map {$self->_ports->{$_}} @{$self->_portsordered};
}

sub nets_and_ports_sorted {
    return Verilog::Netlist::Module::nets_and_ports_sorted(@_);
}

sub new_attr {
    my $self = shift;
    my $clean_text = shift;
    push @{$self->attrs}, $clean_text;
}

sub new_net {
    my $self = shift;
    # @_ params
    # Create a new net under this
    my $netref = new Verilog::Netlist::Net(direction=>'net', data_type=>'wire',
					   @_,
					   module=>$self, );
    $self->_nets($netref->name(), $netref);
    return $netref;
}

sub new_port {
    my $self = shift;
    # @_ params
    # Create a new port under this module
    my $portref = new Verilog::Netlist::Port(@_, module=>$self,);
    $self->_ports($portref->name(), $portref);
    return $portref;
}

sub _link {
    my $self = shift;
    # Ports create nets, so link ports before nets
    foreach my $oref ($self->ports) {
	$oref->_link();
    }
}

sub lint {
    my $self = shift;
    if ($self->netlist->{use_vars}) {
	foreach my $oref ($self->ports) {
	    $oref->lint();
	}
    }
}

sub verilog_text {
    my $self = shift;
    my @out = "modport ".$self->name." (\n";
    my $indent = "   ";
    # Port list
    my $comma="";
    push @out, $indent;
    foreach my $oref ($self->ports_sorted) {
	push @out, $comma, $oref->verilog_text;
	$comma = ", ";
    }
    push @out, ");\n";
    push @out, "endmodport\n";
    return (wantarray ? @out : join('',@out));
}

sub dump {
    my $self = shift;
    my $indent = shift||0;
    my $norecurse = shift;
    print " "x$indent,"ModPort:",$self->name(),"  File:",$self->filename(),"\n";
    if (!$norecurse) {
	foreach my $oref ($self->ports_sorted) {
	    $oref->dump($indent+2);
	}
    }
}

######################################################################
#### Package return
1;
__END__