File Coverage

blib/lib/Verilog/Netlist/PinSelection.pm

Criterion	Covered	Total	%
statement	30	32	93.7
branch	8	14	57.1
condition			n/a
subroutine	8	8	100.0
pod	4	5	80.0
total	50	59	84.7

# Verilog - Verilog Perl Interface
# See copyright, etc in below POD section.
######################################################################

package Verilog::Netlist::PinSelection;

use vars qw($VERSION);
use strict;
use warnings;

$VERSION = '3.427';

######################################################################
#### Methods

## Constructor
sub new {
    my ($class, $netname, $msb, $lsb) = @_;

    my $self = bless({}, $class);
    $self->{_netname} = $netname;
    $self->{_msb} = $msb;
    $self->{_lsb} = $lsb;
    return $self;
}

## Standard accessors
sub netname {
    # ($self, $new) = @_;
    $_[0]->{_netname} = $_[1] if (@_ == 2);
    return $_[0]->{_netname};
}

sub lsb {
    # ($self, $new) = @_;
    $_[0]->{_lsb} = $_[1] if (@_ == 2);
    return $_[0]->{_lsb};
}

sub msb {
    # ($self, $new) = @_;
    $_[0]->{_msb} = $_[1] if (@_ == 2);
    return $_[0]->{_msb};
}

## Member functions
sub bracketed_msb_lsb {
    my $self = shift;
    my $out = "";
    # Handle sized constant numbers (e.g., 7'b0) distinctively
    # but leave unsized constants (msb/lsb undefined) alone.
    if ($self->netname =~ /^'/) {
	$out .= $self->msb + 1 if defined($self->msb);
	$out .= $self->netname;
    } else {
	$out .= $self->netname;
	if (defined($self->msb)) {
	    if ($self->msb == $self->lsb) {
		$out .= "[".$self->msb."]";
	    } else {
		$out .= "[".$self->msb.":".$self->lsb."]";
	    }
	}
    }
    return $out;
}

######################################################################
#### Package return
1;
__END__