line |
stmt |
bran |
cond |
sub |
pod |
time |
code |
1
|
|
|
|
|
|
|
package VIC::PIC::P16F689; |
2
|
1
|
|
|
1
|
|
4
|
use strict; |
|
1
|
|
|
|
|
1
|
|
|
1
|
|
|
|
|
26
|
|
3
|
1
|
|
|
1
|
|
3
|
use warnings; |
|
1
|
|
|
|
|
1
|
|
|
1
|
|
|
|
|
53
|
|
4
|
|
|
|
|
|
|
our $VERSION = '0.31'; |
5
|
|
|
|
|
|
|
$VERSION = eval $VERSION; |
6
|
1
|
|
|
1
|
|
4
|
use Moo; |
|
1
|
|
|
|
|
1
|
|
|
1
|
|
|
|
|
6
|
|
7
|
|
|
|
|
|
|
extends 'VIC::PIC::P16F687'; |
8
|
|
|
|
|
|
|
|
9
|
|
|
|
|
|
|
# role CodeGen |
10
|
|
|
|
|
|
|
has type => (is => 'ro', default => 'p16f689'); |
11
|
|
|
|
|
|
|
has include => (is => 'ro', default => 'p16f689.inc'); |
12
|
|
|
|
|
|
|
|
13
|
|
|
|
|
|
|
# all memory is in bytes |
14
|
|
|
|
|
|
|
has memory => (is => 'ro', default => sub { |
15
|
|
|
|
|
|
|
{ |
16
|
|
|
|
|
|
|
flash => 4096, # words |
17
|
|
|
|
|
|
|
SRAM => 256, |
18
|
|
|
|
|
|
|
EEPROM => 256, |
19
|
|
|
|
|
|
|
} |
20
|
|
|
|
|
|
|
}); |
21
|
|
|
|
|
|
|
has address => (is => 'ro', default => sub { |
22
|
|
|
|
|
|
|
{ |
23
|
|
|
|
|
|
|
isr => [ 0x0004 ], |
24
|
|
|
|
|
|
|
reset => [ 0x0000 ], |
25
|
|
|
|
|
|
|
range => [ 0x0000, 0x0FFF ], |
26
|
|
|
|
|
|
|
} |
27
|
|
|
|
|
|
|
}); |
28
|
|
|
|
|
|
|
|
29
|
|
|
|
|
|
|
has banks => (is => 'ro', default => sub { |
30
|
|
|
|
|
|
|
{ |
31
|
|
|
|
|
|
|
count => 4, |
32
|
|
|
|
|
|
|
size => 0x80, |
33
|
|
|
|
|
|
|
gpr => { |
34
|
|
|
|
|
|
|
0 => [ 0x020, 0x07F], |
35
|
|
|
|
|
|
|
1 => [ 0x0A0, 0x0EF], |
36
|
|
|
|
|
|
|
2 => [ 0x120, 0x16F], |
37
|
|
|
|
|
|
|
}, |
38
|
|
|
|
|
|
|
# remapping of these addresses automatically done by chip |
39
|
|
|
|
|
|
|
common => [0x070, 0x07F], |
40
|
|
|
|
|
|
|
remap => [ |
41
|
|
|
|
|
|
|
[0x0F0, 0x0FF], |
42
|
|
|
|
|
|
|
[0x170, 0x17F], |
43
|
|
|
|
|
|
|
[0x1F0, 0x1FF], |
44
|
|
|
|
|
|
|
], |
45
|
|
|
|
|
|
|
} |
46
|
|
|
|
|
|
|
}); |
47
|
|
|
|
|
|
|
|
48
|
|
|
|
|
|
|
has registers => (is => 'ro', default => sub { |
49
|
|
|
|
|
|
|
{ |
50
|
|
|
|
|
|
|
INDF => [0x000, 0x080, 0x100, 0x180], # indirect addressing |
51
|
|
|
|
|
|
|
TMR0 => [0x001, 0x101], |
52
|
|
|
|
|
|
|
OPTION_REG => [0x081, 0x181], |
53
|
|
|
|
|
|
|
PCL => [0x002, 0x082, 0x102, 0x182], |
54
|
|
|
|
|
|
|
STATUS => [0x003, 0x083, 0x103, 0x183], |
55
|
|
|
|
|
|
|
FSR => [0x004, 0x084, 0x104, 0x184], |
56
|
|
|
|
|
|
|
PORTA => [0x005, 0x105], |
57
|
|
|
|
|
|
|
TRISA => [0x085, 0x185], |
58
|
|
|
|
|
|
|
PORTB => [0x006, 0x106], |
59
|
|
|
|
|
|
|
TRISB => [0x086, 0x186], |
60
|
|
|
|
|
|
|
PORTC => [0x007, 0x107], |
61
|
|
|
|
|
|
|
TRISC => [0x087, 0x187], |
62
|
|
|
|
|
|
|
PCLATH => [0x00A, 0x08A, 0x10A, 0x18A], |
63
|
|
|
|
|
|
|
INTCON => [0x00B, 0x08B, 0x10B, 0x18B], |
64
|
|
|
|
|
|
|
PIR1 => [0x00C], |
65
|
|
|
|
|
|
|
PIE1 => [0x08C], |
66
|
|
|
|
|
|
|
EEDAT => [0x10C], |
67
|
|
|
|
|
|
|
EECON1 => [0x18C], |
68
|
|
|
|
|
|
|
PIR2 => [0x00D], |
69
|
|
|
|
|
|
|
PIE2 => [0x08D], |
70
|
|
|
|
|
|
|
EEADR => [0x10D], |
71
|
|
|
|
|
|
|
EECON2 => [0x18D], # not addressable apparently |
72
|
|
|
|
|
|
|
TMR1L => [0x00E], |
73
|
|
|
|
|
|
|
PCON => [0x08E], |
74
|
|
|
|
|
|
|
EEDATH => [0x10E], |
75
|
|
|
|
|
|
|
TMR1H => [0x00F], |
76
|
|
|
|
|
|
|
OSCCON => [0x08F], |
77
|
|
|
|
|
|
|
EEADRH => [0x10F], |
78
|
|
|
|
|
|
|
T1CON => [0x010], |
79
|
|
|
|
|
|
|
OSCTUNE => [0x090], |
80
|
|
|
|
|
|
|
SSPBUF => [0x013], |
81
|
|
|
|
|
|
|
SSPADD => [0x093], |
82
|
|
|
|
|
|
|
SSPCON => [0x014], |
83
|
|
|
|
|
|
|
SSPSTAT => [0x094], |
84
|
|
|
|
|
|
|
WPUA => [0x095], |
85
|
|
|
|
|
|
|
WPUB => [0x115], |
86
|
|
|
|
|
|
|
IOCA => [0x096], |
87
|
|
|
|
|
|
|
IOCB => [0x116], |
88
|
|
|
|
|
|
|
WDTCON => [0x097], |
89
|
|
|
|
|
|
|
RCSTA => [0x018], |
90
|
|
|
|
|
|
|
TXSTA => [0x098], |
91
|
|
|
|
|
|
|
VRCON => [0x118], |
92
|
|
|
|
|
|
|
TXREG => [0x019], |
93
|
|
|
|
|
|
|
SPBRG => [0x099], |
94
|
|
|
|
|
|
|
CM1CON0 => [0x119], |
95
|
|
|
|
|
|
|
RCREG => [0x01A], |
96
|
|
|
|
|
|
|
SPBRGH => [0x09A], |
97
|
|
|
|
|
|
|
CM2CON0 => [0x11A], |
98
|
|
|
|
|
|
|
BAUDCTL => [0x09B], |
99
|
|
|
|
|
|
|
CM2CON1 => [0x11B], |
100
|
|
|
|
|
|
|
ADRESH => [0x01E], |
101
|
|
|
|
|
|
|
ADRESL => [0x09E], |
102
|
|
|
|
|
|
|
ANSEL => [0x11E], |
103
|
|
|
|
|
|
|
SRCON => [0x19E], |
104
|
|
|
|
|
|
|
ADCON0 => [0x01F], |
105
|
|
|
|
|
|
|
ADCON1 => [0x09F], |
106
|
|
|
|
|
|
|
ANSELH => [0x11F], |
107
|
|
|
|
|
|
|
} |
108
|
|
|
|
|
|
|
}); |
109
|
|
|
|
|
|
|
|
110
|
|
|
|
|
|
|
1; |
111
|
|
|
|
|
|
|
__END__ |