File Coverage

blib/lib/HiPi/Constant.pm
Criterion Covered Total %
statement 36 36 100.0
branch 2 2 100.0
condition n/a
subroutine 7 7 100.0
pod 0 3 0.0
total 45 48 93.7


line stmt bran cond sub pod time code
1             ##########################################################################################
2             # Distribution : HiPi Modules for Raspberry Pi
3             # File : lib/HiPi/Constant.pm
4             # Description : Constants for HiPi
5             # Copyright : Copyright (c) 2013-2017 Mark Dootson
6             # License : This is free software; you can redistribute it and/or modify it under
7             # the same terms as the Perl 5 programming language system itself.
8             #########################################################################################
9              
10             package HiPi::Constant;
11              
12             #########################################################################################
13 5     5   31 use strict;
  5         9  
  5         129  
14 5     5   21 use warnings;
  5         11  
  5         123  
15 5     5   22 use parent qw( Exporter );
  5         8  
  5         19  
16 5     5   2181 use HiPi::RaspberryPi;
  5         41  
  5         10169  
17              
18             our $VERSION ='0.80';
19              
20             our @EXPORT_OK = ( qw( hipi_export_ok hipi_export_constants hipi_export_tags ) );
21             our %EXPORT_TAGS = ( hipi => \@EXPORT_OK );
22              
23             my $MCP_DAC_RESOLUTION_08 = 0x010;
24             my $MCP_DAC_RESOLUTION_10 = 0x020;
25             my $MCP_DAC_RESOLUTION_12 = 0x030;
26             my $MCP_DAC_DUAL_CHANNEL = 0x001;
27             my $MCP_DAC_CAN_BUFFER = 0x002;
28              
29             my $legacyboard = ( HiPi::RaspberryPi::board_type() == 1 ) ? 1 : 0;
30              
31             my $const = {
32             i2c => {
33             I2C_READMODE_SYSTEM => 0,
34             I2C_READMODE_REPEATED_START => 1,
35             I2C_READMODE_START_STOP => 2,
36            
37             I2C_SCANMODE_AUTO => 0,
38             I2C_SCANMODE_QUICK => 1,
39             I2C_SCANMODE_READ => 2,
40            
41             I2C_RETRIES => 0x0701,
42             I2C_TIMEOUT => 0x0702,
43             I2C_SLAVE => 0x0703,
44             I2C_TENBIT => 0x0704,
45             I2C_FUNCS => 0x0705,
46             I2C_SLAVE_FORCE => 0x0706,
47             I2C_RDWR => 0x0707,
48             I2C_PEC => 0x0708,
49             I2C_SMBUS => 0x0720,
50            
51             I2C_M_TEN => 0x0010,
52             I2C_M_RD => 0x0001,
53             I2C_M_NOSTART => 0x4000,
54             I2C_M_REV_DIR_ADDR => 0x2000,
55             I2C_M_IGNORE_NAK => 0x1000,
56             I2C_M_NO_RD_ACK => 0x0800,
57             I2C_M_RECV_LEN => 0x0400,
58            
59             I2C0_SDA => ( $legacyboard ) ? 0 : 28,
60             I2C0_SCL => ( $legacyboard ) ? 1 : 29,
61             I2C1_SDA => 2,
62             I2C1_SCL => 3,
63             I2C_SDA => ( $legacyboard ) ? 0 : 2,
64             I2C_SCL => ( $legacyboard ) ? 1 : 3,
65             ID_SD => 0,
66             ID_SC => 1,
67             },
68            
69             rpi => {
70             RPI_PIN_3 => ( $legacyboard ) ? 0 : 2,
71             RPI_PIN_5 => ( $legacyboard ) ? 1 : 3,
72             RPI_PIN_7 => 4,
73             RPI_PIN_8 => 14,
74             RPI_PIN_10 => 15,
75             RPI_PIN_11 => 17,
76             RPI_PIN_12 => 18,
77             RPI_PIN_13 => 27,
78             RPI_PIN_15 => 22,
79             RPI_PIN_16 => 23,
80             RPI_PIN_18 => 24,
81             RPI_PIN_19 => 10,
82             RPI_PIN_21 => 9,
83             RPI_PIN_22 => 25,
84             RPI_PIN_23 => 11,
85             RPI_PIN_24 => 8,
86             RPI_PIN_26 => 7,
87             RPI_PIN_27 => 0,
88             RPI_PIN_28 => 1,
89             RPI_PIN_29 => 5,
90             RPI_PIN_31 => 6,
91             RPI_PIN_32 => 12,
92             RPI_PIN_33 => 13,
93             RPI_PIN_35 => 19,
94             RPI_PIN_36 => 16,
95             RPI_PIN_37 => 26,
96             RPI_PIN_38 => 20,
97             RPI_PIN_40 => 21,
98            
99             RPI_OUTPUT => 1,
100             RPI_INPUT => 0,
101            
102             RPI_MODE_INPUT => 0,
103             RPI_MODE_OUTPUT => 1,
104             RPI_MODE_ALT0 => 4,
105             RPI_MODE_ALT1 => 5,
106             RPI_MODE_ALT2 => 6,
107             RPI_MODE_ALT3 => 7,
108             RPI_MODE_ALT4 => 3,
109             RPI_MODE_ALT5 => 2,
110            
111             RPI_INT_NONE => 0x00,
112             RPI_INT_FALL => 0x01,
113             RPI_INT_RISE => 0x02,
114             RPI_INT_BOTH => 0x03,
115             RPI_INT_AFALL => 0x04,
116             RPI_INT_ARISE => 0x08,
117             RPI_INT_HIGH => 0x10,
118             RPI_INT_LOW => 0x20,
119            
120             # legacy
121             RPI_PINMODE_INPT => 0,
122             RPI_PINMODE_OUTP => 1,
123             RPI_PINMODE_ALT0 => 4,
124             RPI_PINMODE_ALT1 => 5,
125             RPI_PINMODE_ALT2 => 6,
126             RPI_PINMODE_ALT3 => 7,
127             RPI_PINMODE_ALT4 => 3,
128             RPI_PINMODE_ALT5 => 2,
129            
130             RPI_HIGH => 1,
131             RPI_LOW => 0,
132            
133             RPI_BOARD_TYPE_1 => 1,
134             RPI_BOARD_TYPE_2 => 2,
135             RPI_BOARD_TYPE_3 => 3,
136            
137             RPI_PUD_NULL => -1,
138             RPI_PUD_OFF => 0,
139             RPI_PUD_DOWN => 1,
140             RPI_PUD_UP => 2,
141             RPI_PUD_UNSET => 0x08,
142            
143             RPI_BOARD_REVISION => HiPi::RaspberryPi::board_type(),
144            
145             DEV_GPIO_PIN_STATUS_NONE => 0x00,
146             DEV_GPIO_PIN_STATUS_EXPORTED => 0x01,
147             },
148            
149             spi => {
150             SPI_CPHA => 0x01,
151             SPI_CPOL => 0x02,
152             SPI_MODE_0 => 0x00,
153             SPI_MODE_1 => 0x01,
154             SPI_MODE_2 => 0x02,
155             SPI_MODE_3 => 0x03,
156             SPI_CS_HIGH => 0x04,
157             SPI_LSB_FIRST => 0x08,
158             SPI_3WIRE => 0x10,
159             SPI_LOOP => 0x20,
160             SPI_NO_CS => 0x40,
161             SPI_READY => 0x80,
162             SPI_SPEED_KHZ_500 => 500000,
163             SPI_SPEED_MHZ_1 => 1000000,
164             SPI_SPEED_MHZ_2 => 2000000,
165             SPI_SPEED_MHZ_4 => 4000000,
166             SPI_SPEED_MHZ_8 => 8000000,
167             SPI_SPEED_MHZ_16 => 16000000,
168             SPI_SPEED_MHZ_32 => 32000000,
169             },
170            
171             mcp23x17 => {
172             MCP23S17_A0 => 0x1000,
173             MCP23S17_A1 => 0x1001,
174             MCP23S17_A2 => 0x1002,
175             MCP23S17_A3 => 0x1003,
176             MCP23S17_A4 => 0x1004,
177             MCP23S17_A5 => 0x1005,
178             MCP23S17_A6 => 0x1006,
179             MCP23S17_A7 => 0x1007,
180             MCP23S17_B0 => 0x1010,
181             MCP23S17_B1 => 0x1011,
182             MCP23S17_B2 => 0x1012,
183             MCP23S17_B3 => 0x1013,
184             MCP23S17_B4 => 0x1014,
185             MCP23S17_B5 => 0x1015,
186             MCP23S17_B6 => 0x1016,
187             MCP23S17_B7 => 0x1017,
188            
189             MCP23S17_BANK => 7,
190             MCP23S17_MIRROR => 6,
191             MCP23S17_SEQOP => 5,
192             MCP23S17_DISSLW => 4,
193             MCP23S17_HAEN => 3,
194             MCP23S17_ODR => 2,
195             MCP23S17_INTPOL => 1,
196            
197             MCP23S17_INPUT => 1,
198             MCP23S17_OUTPUT => 0,
199            
200             MCP23S17_HIGH => 1,
201             MCP23S17_LOW => 0,
202            
203             MCP23017_A0 => 0x1000,
204             MCP23017_A1 => 0x1001,
205             MCP23017_A2 => 0x1002,
206             MCP23017_A3 => 0x1003,
207             MCP23017_A4 => 0x1004,
208             MCP23017_A5 => 0x1005,
209             MCP23017_A6 => 0x1006,
210             MCP23017_A7 => 0x1007,
211             MCP23017_B0 => 0x1010,
212             MCP23017_B1 => 0x1011,
213             MCP23017_B2 => 0x1012,
214             MCP23017_B3 => 0x1013,
215             MCP23017_B4 => 0x1014,
216             MCP23017_B5 => 0x1015,
217             MCP23017_B6 => 0x1016,
218             MCP23017_B7 => 0x1017,
219            
220             MCP23017_BANK => 7,
221             MCP23017_MIRROR => 6,
222             MCP23017_SEQOP => 5,
223             MCP23017_DISSLW => 4,
224             MCP23017_HAEN => 3,
225             MCP23017_ODR => 2,
226             MCP23017_INTPOL => 1,
227            
228             MCP23017_INPUT => 1,
229             MCP23017_OUTPUT => 0,
230            
231             MCP23017_HIGH => 1,
232             MCP23017_LOW => 0,
233            
234             MCP_PIN_A0 => 'A0',
235             MCP_PIN_A1 => 'A1',
236             MCP_PIN_A2 => 'A2',
237             MCP_PIN_A3 => 'A3',
238             MCP_PIN_A4 => 'A4',
239             MCP_PIN_A5 => 'A5',
240             MCP_PIN_A6 => 'A6',
241             MCP_PIN_A7 => 'A7',
242             MCP_PIN_B0 => 'B0',
243             MCP_PIN_B1 => 'B1',
244             MCP_PIN_B2 => 'B2',
245             MCP_PIN_B3 => 'B3',
246             MCP_PIN_B4 => 'B4',
247             MCP_PIN_B5 => 'B5',
248             MCP_PIN_B6 => 'B6',
249             MCP_PIN_B7 => 'B7',
250             },
251            
252             mpl3115a2 => {
253             MPL_REG_STATUS => 0x00,
254             MPL_REG_OUT_P_MSB => 0x01,
255             MPL_REG_OUT_P_CSB => 0x02,
256             MPL_REG_OUT_P_LSB => 0x03,
257             MPL_REG_OUT_T_MSB => 0x04,
258             MPL_REG_OUT_T_LSB => 0x05,
259             MPL_REG_DR_STATUS => 0x06,
260             MPL_REG_OUT_P_DELTA_MSB => 0x07,
261             MPL_REG_OUT_P_DELTA_CSB => 0x08,
262             MPL_REG_OUT_P_DELTA_LSB => 0x09,
263             MPL_REG_OUT_T_DELTA_MSB => 0x0A,
264             MPL_REG_OUT_T_DELTA_LSB => 0x0B,
265             MPL_REG_WHO_AM_I => 0x0C,
266             MPL_REG_F_STATUS => 0x0D,
267             MPL_REG_F_DATA => 0x0E,
268             MPL_REG_F_SETUP => 0x0F,
269             MPL_REG_TIME_DLY => 0x10,
270             MPL_REG_SYSMOD => 0x11,
271             MPL_REG_INT_SOURCE => 0x12,
272             MPL_REG_PT_DATA_CFG => 0x13,
273             MPL_REG_BAR_IN_MSB => 0x14,
274             MPL_REG_MAR_IN_LSB => 0x15,
275             MPL_REG_P_TGT_MSB => 0x16,
276             MPL_REG_P_TGT_LSB => 0x17,
277             MPL_REG_T_TGT => 0x18,
278             MPL_REG_P_WND_MSB => 0x19,
279             MPL_REG_P_WND_LSB => 0x1A,
280             MPL_REG_T_WND => 0x1B,
281             MPL_REG_P_MIN_MSB => 0x1C,
282             MPL_REG_P_MIN_CSB => 0x1D,
283             MPL_REG_P_MIN_LSB => 0x1E,
284             MPL_REG_T_MIN_MSB => 0x1F,
285             MPL_REG_T_MIN_LSB => 0x20,
286             MPL_REG_P_MAX_MSB => 0x21,
287             MPL_REG_P_MAX_CSB => 0x22,
288             MPL_REG_P_MAX_LSB => 0x23,
289             MPL_REG_T_MAX_MSB => 0x24,
290             MPL_REG_T_MAX_LSB => 0x25,
291             MPL_REG_CTRL_REG1 => 0x26,
292             MPL_REG_CTRL_REG2 => 0x27,
293             MPL_REG_CTRL_REG3 => 0x28,
294             MPL_REG_CTRL_REG4 => 0x29,
295             MPL_REG_CTRL_REG5 => 0x2A,
296             MPL_REG_OFF_P => 0x2B,
297             MPL_REG_OFF_T => 0x2C,
298             MPL_REG_OFF_H => 0x2D,
299            
300             MPL_CTRL_REG1_SBYB => 0x01,
301             MPL_CTRL_REG1_OST => 0x02,
302             MPL_CTRL_REG1_RST => 0x04,
303             MPL_CTRL_REG1_OS0 => 0x08,
304             MPL_CTRL_REG1_OS1 => 0x10,
305             MPL_CTRL_REG1_OS2 => 0x20,
306             MPL_CTRL_REG1_RAW => 0x40,
307             MPL_CTRL_REG1_ALT => 0x80,
308            
309             MPL_CTRL_REG1_MASK => 0xFF,
310            
311             MPL_CTRL_REG2_ST0 => 0x01,
312             MPL_CTRL_REG2_ST1 => 0x02,
313             MPL_CTRL_REG2_ST2 => 0x04,
314             MPL_CTRL_REG2_ST3 => 0x08,
315             MPL_CTRL_REG2_ALARM_SEL => 0x10,
316             MPL_CTRL_REG2_LOAD_OUTPUT => 0x20,
317            
318             MPL_CTRL_REG2_MASK => 0x3F,
319            
320             MPL_CTRL_REG3_PP_0D2 => 0x01,
321             MPL_CTRL_REG3_IPOL2 => 0x02,
322             MPL_CTRL_REG3_PP_OD1 => 0x10,
323             MPL_CTRL_REG3_IPOL1 => 0x20,
324            
325             MPL_CTRL_REG3_MASK => 0x33,
326            
327             MPL_CTRL_REG4_INT_EN_DRDY => 0x80,
328             MPL_CTRL_REG4_INT_EN_FIFO => 0x40,
329             MPL_CTRL_REG4_INT_EN_PW => 0x20,
330             MPL_CTRL_REG4_INT_EN_TW => 0x10,
331             MPL_CTRL_REG4_INT_EN_PTH => 0x08,
332             MPL_CTRL_REG4_INT_EN_TTH => 0x04,
333             MPL_CTRL_REG4_INT_EN_PCHG => 0x02,
334             MPL_CTRL_REG4_INT_EN_TCHG => 0x01,
335            
336             MPL_CTRL_REG4_MASK => 0xFF,
337            
338             MPL_INTREGS_DRDY => 0x80,
339             MPL_INTREGS_FIFO => 0x40,
340             MPL_INTREGS_PW => 0x20,
341             MPL_INTREGS_TW => 0x10,
342             MPL_INTREGS_PTH => 0x08,
343             MPL_INTREGS_TTH => 0x04,
344             MPL_INTREGS_PCHG => 0x02,
345             MPL_INTREGS_TCHG => 0x01,
346            
347             MPL_INTREGS_MASK => 0xFF,
348            
349             MPL_DR_STATUS_PTOW => 0x80,
350             MPL_DR_STATUS_POW => 0x40,
351             MPL_DR_STATUS_TOW => 0x20,
352             MPL_DR_STATUS_PTDR => 0x08,
353             MPL_DR_STATUS_PDR => 0x04,
354             MPL_DR_STATUS_TDR => 0x02,
355            
356             MPL_DR_STATUS_MASK => 0xEE,
357            
358             MPL_F_STATUS_F_OVF => 0x80,
359             MPL_F_STATUS_F_WMRK_FLAG => 0x40,
360             MPL_F_STATUS_F_CNT5 => 0x20,
361             MPL_F_STATUS_F_CNT4 => 0x10,
362             MPL_F_STATUS_F_CNT3 => 0x08,
363             MPL_F_STATUS_F_CNT2 => 0x04,
364             MPL_F_STATUS_F_CNT1 => 0x02,
365             MPL_F_STATUS_F_CNT0 => 0x01,
366            
367             MPL_F_STATUS_MASK => 0xFF,
368            
369             MPL_PT_DATA_CFG_DREM => 0x04,
370             MPL_PT_DATA_CFG_PDEFE => 0x02,
371             MPL_PT_DATA_CFG_TDEFE => 0x01,
372            
373             MPL_PT_DATA_CFG_MASK => 0x07,
374            
375             MPL_BIT_SBYB => 0,
376             MPL_BIT_OST => 1,
377             MPL_BIT_RST => 2,
378             MPL_BIT_OS0 => 3,
379             MPL_BIT_OS1 => 4,
380             MPL_BIT_OS2 => 5,
381             MPL_BIT_RAW => 6,
382             MPL_BIT_ALT => 7,
383            
384             MPL_BIT_ST0 => 0,
385             MPL_BIT_ST1 => 1,
386             MPL_BIT_ST2 => 2,
387             MPL_BIT_ST3 => 3,
388             MPL_BIT_ALARM_SEL => 4,
389             MPL_BIT_LOAD_OUTPUT => 5,
390            
391             MPL_BIT_PP_0D2 => 0,
392             MPL_BIT_IPOL2 => 1,
393             MPL_BIT_PP_OD1 => 4,
394             MPL_BIT_IPOL1 => 5,
395            
396             # interrupt bits for CTRL_REG5,
397             # INT_SOURCE
398            
399             MPL_BIT_DRDY => 7,
400             MPL_BIT_FIFO => 6,
401             MPL_BIT_PW => 5,
402             MPL_BIT_TW => 4,
403             MPL_BIT_PTH => 3,
404             MPL_BIT_TTH => 2,
405             MPL_BIT_PCHG => 1,
406             MPL_BIT_TCHG => 0,
407            
408             MPL_BIT_PTOW => 7,
409             MPL_BIT_POW => 6,
410             MPL_BIT_TOW => 5,
411             MPL_BIT_PTDR => 3,
412             MPL_BIT_PDR => 2,
413             MPL_BIT_TDR => 1,
414            
415             MPL_BIT_F_OVF => 7,
416             MPL_BIT_F_WMRK_FLAG => 6,
417             MPL_BIT_F_CNT5 => 5,
418             MPL_BIT_F_CNT4 => 4,
419             MPL_BIT_F_CNT3 => 3,
420             MPL_BIT_F_CNT2 => 2,
421             MPL_BIT_F_CNT1 => 1,
422             MPL_BIT_F_CNT0 => 0,
423            
424             MPL_BIT_DREM => 2,
425             MPL_BIT_PDEFE => 1,
426             MPL_BIT_TDEFE => 0,
427            
428            
429             MPL_OSREAD_DELAY => 1060, # left for compatibility with code that uses it.
430            
431             MPL_FUNC_ALTITUDE => 1,
432             MPL_FUNC_PRESSURE => 2,
433             MPL3115A2_ID => 0xC4,
434            
435            
436             MPL_CONTROL_MASK => 0b00111000, #128 oversampling
437             MPL_BYTE_MASK => 0xFF,
438             MPL_WORD_MASK => 0xFFFF,
439            
440             MPL_OVERSAMPLE_1 => 0b00000000,
441             MPL_OVERSAMPLE_2 => 0b00001000,
442             MPL_OVERSAMPLE_4 => 0b00010000,
443             MPL_OVERSAMPLE_8 => 0b00011000,
444             MPL_OVERSAMPLE_16 => 0b00100000,
445             MPL_OVERSAMPLE_32 => 0b00101000,
446             MPL_OVERSAMPLE_64 => 0b00110000,
447             MPL_OVERSAMPLE_128 => 0b00111000,
448            
449             MPL_OVERSAMPLE_MASK => 0b00111000,
450            
451             MPL_BB_I2C_PERI_0 => 0x10,
452             MPL_BB_I2C_PERI_1 => 0x20,
453            
454             },
455            
456             lcd => {
457             HD44780_CLEAR_DISPLAY => 0x01,
458             HD44780_HOME_UNSHIFT => 0x02,
459             HD44780_CURSOR_MODE_LEFT => 0x04,
460             HD44780_CURSOR_MODE_LEFT_SHIFT => 0x05,
461             HD44780_CURSOR_MODE_RIGHT => 0x06,
462             HD44780_CURSOR_MODE_RIGHT_SHIFT => 0x07,
463             HD44780_DISPLAY_OFF => 0x08,
464            
465             HD44780_DISPLAY_ON => 0x0C,
466             HD44780_CURSOR_OFF => 0x0C,
467             HD44780_CURSOR_UNDERLINE => 0x0E,
468             HD44780_CURSOR_BLINK => 0x0F,
469            
470             HD44780_SHIFT_CURSOR_LEFT => 0x10,
471             HD44780_SHIFT_CURSOR_RIGHT => 0x14,
472             HD44780_SHIFT_DISPLAY_LEFT => 0x18,
473             HD44780_SHIFT_DISPLAY_RIGHT => 0x1C,
474            
475             HD44780_CURSOR_POSITION => 0x80,
476            
477             SRX_CURSOR_OFF => 0x0C,
478             SRX_CURSOR_BLINK => 0x0F,
479             SRX_CURSOR_UNDERLINE => 0x0E,
480            
481             HTV2_END_SERIALRX_COMMAND => chr(0xFF),
482            
483             HTV2_BAUD_2400 => 0,
484             HTV2_BAUD_4800 => 1,
485             HTV2_BAUD_9600 => 2,
486             HTV2_BAUD_14400 => 3,
487             HTV2_BAUD_19200 => 4,
488             HTV2_BAUD_28800 => 5,
489             HTV2_BAUD_57600 => 6,
490             HTV2_BAUD_115200 => 7,
491            
492             HTV2_CMD_PRINT => 1,
493             HTV2_CMD_SET_CURSOR_POS => 2,
494             HTV2_CMD_CLEAR_LINE => 3,
495             HTV2_CMD_CLEAR_DISPLAY => 4,
496             HTV2_CMD_LCD_TYPE => 5,
497             HTV2_CMD_HD44780_CMD => 6,
498             HTV2_CMD_BACKLIGHT => 7,
499             HTV2_CMD_WRITE_CHAR => 10,
500             HTV2_CMD_I2C_ADDRESS => 32,
501             HTV2_CMD_BAUD_RATE => 33,
502             HTV2_CMD_CUSTOM_CHAR => 64,
503            
504             SLCD_START_COMMAND => chr(0xFE),
505             SLCD_SPECIAL_COMMAND => chr(0x7C),
506             },
507            
508             hrf69 => {
509             RF69_REG_FIFO => 0x00,
510             RF69_REG_OPMODE => 0x01,
511             RF69_REG_REGDATAMODUL => 0x02,
512             RF69_REG_BITRATEMSB => 0x03,
513             RF69_REG_BITRATELSB => 0x04,
514             RF69_REG_FDEVMSB => 0x05,
515             RF69_REG_FDEVLSB => 0x06,
516             RF69_REG_FRMSB => 0x07,
517             RF69_REG_FRMID => 0x08,
518             RF69_REG_FRLSB => 0x09,
519             RF69_REG_CALLIB => 0x0A,
520             RF69_REG_AFCCTRL => 0x0B,
521             RF69_REG_LISTEN1 => 0x0D,
522             RF69_REG_LISTEN2 => 0x0E,
523             RF69_REG_LISTEN3 => 0x0F,
524             RF69_REG_VERSION => 0x10,
525             RF69_REG_PALEVEL => 0x11,
526             RF69_REG_PARAMP => 0x12,
527             RF69_REG_OCP => 0x13,
528             RF69_REG_LNA => 0x18,
529             RF69_REG_RXBW => 0x19,
530             RF69_REG_AFCBW => 0x1A,
531             RF69_REG_OOKPEAK => 0x1B,
532             RF69_REG_OOKAVG => 0x1C,
533             RF69_REG_OOKFIX => 0x1D,
534             RF69_REG_AFCFEI => 0x1E,
535             RF69_REG_AFCMSB => 0x1F,
536             RF69_REG_AFCLSB => 0x20,
537             RF69_REG_FEIMSB => 0x21,
538             RF69_REG_FEILSB => 0x22,
539             RF69_REG_RSSICONFIG => 0x23,
540             RF69_REG_RSSIVALUE => 0x24,
541             RF69_REG_DIOMAPPING1 => 0x25,
542             RF69_REG_DIOMAPPING2 => 0x26,
543             RF69_REG_IRQFLAGS1 => 0x27,
544             RF69_REG_IRQFLAGS2 => 0x28,
545             RF69_REG_RSSITHRESH => 0x29,
546             RF69_REG_RXTIMEOUT1 => 0x2A,
547             RF69_REG_RXTIMEOUT2 => 0x2B,
548             RF69_REG_PREAMBLEMSB => 0x2C,
549             RF69_REG_PREAMBLELSB => 0x2D,
550             RF69_REG_SYNCCONFIG => 0x2E,
551             RF69_REG_SYNCVALUE1 => 0x2F,
552             RF69_REG_SYNCVALUE2 => 0x30,
553             RF69_REG_SYNCVALUE3 => 0x31,
554             RF69_REG_SYNCVALUE4 => 0x32,
555             RF69_REG_SYNCVALUE5 => 0x33,
556             RF69_REG_SYNCVALUE6 => 0x34,
557             RF69_REG_SYNCVALUE7 => 0x35,
558             RF69_REG_SYNCVALUE8 => 0x36,
559             RF69_REG_PACKETCONFIG1 => 0x37,
560             RF69_REG_PAYLOADLEN => 0x38,
561             RF69_REG_NODEADDRESS => 0x39,
562             RF69_REG_BROADCASTADDRESS => 0x3A,
563             RF69_REG_AUTOMODES => 0x3B,
564             RF69_REG_FIFOTHRESH => 0x3C,
565             RF69_REG_PACKETCONFIG2 => 0x3D,
566             RF69_REG_AESKEY1 => 0x3E,
567             RF69_REG_AESKEY2 => 0x3F,
568             RF69_REG_AESKEY3 => 0x40,
569             RF69_REG_AESKEY4 => 0x41,
570             RF69_REG_AESKEY5 => 0x42,
571             RF69_REG_AESKEY6 => 0x43,
572             RF69_REG_AESKEY7 => 0x44,
573             RF69_REG_AESKEY8 => 0x45,
574             RF69_REG_AESKEY9 => 0x46,
575             RF69_REG_AESKEY10 => 0x47,
576             RF69_REG_AESKEY11 => 0x48,
577             RF69_REG_AESKEY12 => 0x49,
578             RF69_REG_AESKEY13 => 0x4A,
579             RF69_REG_AESKEY14 => 0x4B,
580             RF69_REG_AESKEY15 => 0x4C,
581             RF69_REG_AESKEY16 => 0x4D,
582             RF69_REG_TEMP1 => 0x4E,
583             RF69_REG_TEMP2 => 0x4F,
584            
585             RF69_REG_TESTLNA => 0x58,
586             RF69_REG_TESTPA1 => 0x5A,
587             RF69_REG_TESTPA2 => 0x5C,
588             RF69_REG_TESTDAGC => 0x6F,
589            
590             RF69_REG_TESTAFC => 0x71,
591            
592             RF69_MASK_REG_WRITE => 0x80,
593            
594             RF69_TRUE => 1,
595             RF69_FALSE => 0,
596            
597             RF69_MASK_OPMODE_SEQOFF => 0x80,
598             RF69_MASK_OPMODE_LISTENON => 0x40,
599             RF69_MASK_OPMODE_LISTENABORT => 0x20,
600             RF69_MASK_OPMODE_RX => 0x10,
601             RF69_MASK_OPMODE_TX => 0x0C,
602             RF69_MASK_OPMODE_FS => 0x08,
603             RF69_MASK_OPMODE_SB => 0x04,
604            
605             RF69_MASK_MODEREADY => 0x80,
606             RF69_MASK_FIFONOTEMPTY => 0x40,
607            
608             RF69_MASK_FIFOLEVEL => 0x20,
609             RF69_MASK_FIFOOVERRUN => 0x10,
610             RF69_MASK_PACKETSENT => 0x08,
611             RF69_MASK_TXREADY => 0x20,
612             RF69_MASK_PACKETMODE => 0x60,
613             RF69_MASK_MODULATION => 0x18,
614             RF69_MASK_PAYLOADRDY => 0x04,
615             RF69_MASK_REGDATAMODUL_FSK => 0x00, # Modulation scheme FSK
616             RF69_MASK_REGDATAMODUL_OOK => 0x08, # Modulation scheme OOK
617            
618             RF69_VAL_AFCCTRLS => 0x00, # standard AFC routine
619             RF69_VAL_AFCCTRLI => 0x20, # improved AFC routine
620             RF69_VAL_LNA50 => 0x08, # LNA input impedance 50 ohms
621             RF69_VAL_LNA50G => 0x0E, # LNA input impedance 50 ohms, LNA gain -> 48db
622             RF69_VAL_LNA200 => 0x88, # LNA input impedance 200 ohms
623             RF69_VAL_RXBW60 => 0x43, # channel filter bandwidth 10kHz -> 60kHz page:26
624             RF69_VAL_RXBW120 => 0x41, # channel filter bandwidth 120kHz
625             RF69_VAL_AFCFEIRX => 0x04, # AFC is performed each time RX mode is entered
626             RF69_VAL_RSSITHRESH220 => 0xDC, # RSSI threshold => 0xE4 -> => 0xDC (220)
627             RF69_VAL_PREAMBLELSB3 => 0x03, # preamble size LSB 3
628             RF69_VAL_PREAMBLELSB5 => 0x05, # preamble size LSB 5
629             },
630            
631             mcp3adc => {
632             # msb = channels, lsb = hsb return value mask - 10 bit = 0x03, 12 bit = 0x0F
633             MCP3004 => 0x0403, # 4 channels, 10 bit
634             MCP3008 => 0x0803, # 8 channels, 10 bit
635             MCP3204 => 0x040F, # 4 channels, 12 bit
636             MCP3208 => 0x080F, # 8 channels, 12 bit
637            
638             MCP3ADC_CHAN_0 => 0b00001000, # single-ended CH0
639             MCP3ADC_CHAN_1 => 0b00001001, # single-ended CH1
640             MCP3ADC_CHAN_2 => 0b00001010, # single-ended CH2
641             MCP3ADC_CHAN_3 => 0b00001011, # single-ended CH3
642             MCP3ADC_CHAN_4 => 0b00001100, # single-ended CH4
643             MCP3ADC_CHAN_5 => 0b00001101, # single-ended CH5
644             MCP3ADC_CHAN_6 => 0b00001110, # single-ended CH6
645             MCP3ADC_CHAN_7 => 0b00001111, # single-ended CH7
646             MCP3ADC_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
647             MCP3ADC_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
648             MCP3ADC_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
649             MCP3ADC_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
650             MCP3ADC_DIFF_4_5 => 0b00000100, # differential +CH4 -CH5
651             MCP3ADC_DIFF_5_4 => 0b00000101, # differential -CH4 +CH5
652             MCP3ADC_DIFF_6_7 => 0b00000110, # differential +CH6 -CH7
653             MCP3ADC_DIFF_7_6 => 0b00000111, # differential -CH6 +CH7
654            
655             MCP3008_S0 => 0b00001000, # single-ended CH0
656             MCP3008_S1 => 0b00001001, # single-ended CH1
657             MCP3008_S2 => 0b00001010, # single-ended CH2
658             MCP3008_S3 => 0b00001011, # single-ended CH3
659             MCP3008_S4 => 0b00001100, # single-ended CH4
660             MCP3008_S5 => 0b00001101, # single-ended CH5
661             MCP3008_S6 => 0b00001110, # single-ended CH6
662             MCP3008_S7 => 0b00001111, # single-ended CH7
663             MCP3008_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
664             MCP3008_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
665             MCP3008_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
666             MCP3008_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
667             MCP3008_DIFF_4_5 => 0b00000100, # differential +CH4 -CH5
668             MCP3008_DIFF_5_4 => 0b00000101, # differential -CH4 +CH5
669             MCP3008_DIFF_6_7 => 0b00000110, # differential +CH6 -CH7
670             MCP3008_DIFF_7_6 => 0b00000110, # differential -CH6 +CH7
671            
672             MCP3208_S0 => 0b00001000, # single-ended CH0
673             MCP3208_S1 => 0b00001001, # single-ended CH1
674             MCP3208_S2 => 0b00001010, # single-ended CH2
675             MCP3208_S3 => 0b00001011, # single-ended CH3
676             MCP3208_S4 => 0b00001100, # single-ended CH4
677             MCP3208_S5 => 0b00001101, # single-ended CH5
678             MCP3208_S6 => 0b00001110, # single-ended CH6
679             MCP3208_S7 => 0b00001111, # single-ended CH7
680             MCP3208_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
681             MCP3208_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
682             MCP3208_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
683             MCP3208_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
684             MCP3208_DIFF_4_5 => 0b00000100, # differential +CH4 -CH5
685             MCP3208_DIFF_5_4 => 0b00000101, # differential -CH4 +CH5
686             MCP3208_DIFF_6_7 => 0b00000110, # differential +CH6 -CH7
687             MCP3208_DIFF_7_6 => 0b00000110, # differential -CH6 +CH7
688            
689             MCP3004_S0 => 0b00001000, # single-ended CH0
690             MCP3004_S1 => 0b00001001, # single-ended CH1
691             MCP3004_S2 => 0b00001010, # single-ended CH2
692             MCP3004_S3 => 0b00001011, # single-ended CH3
693             MCP3004_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
694             MCP3004_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
695             MCP3004_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
696             MCP3004_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
697            
698             MCP3204_S0 => 0b00001000, # single-ended CH0
699             MCP3204_S1 => 0b00001001, # single-ended CH1
700             MCP3204_S2 => 0b00001010, # single-ended CH2
701             MCP3204_S3 => 0b00001011, # single-ended CH3
702             MCP3204_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
703             MCP3204_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
704             MCP3204_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
705             MCP3204_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
706            
707             },
708            
709             mcp4dac => {
710             MCP_DAC_RESOLUTION_08 => $MCP_DAC_RESOLUTION_08,
711             MCP_DAC_RESOLUTION_10 => $MCP_DAC_RESOLUTION_10,
712             MCP_DAC_RESOLUTION_12 => $MCP_DAC_RESOLUTION_12,
713             MCP_DAC_CAN_BUFFER => $MCP_DAC_CAN_BUFFER,
714             MCP_DAC_DUAL_CHANNEL => $MCP_DAC_DUAL_CHANNEL,
715            
716             MCP_DAC_CHANNEL_A => 0x00,
717             MCP_DAC_CHANNEL_B => 0x8000,
718             MCP_DAC_BUFFER => 0x4000,
719             MCP_DAC_GAIN => 0x00,
720             MCP_DAC_NO_GAIN => 0x2000,
721             MCP_DAC_LIVE => 0x1000,
722             MCP_DAC_SHUTDOWN => 0x00,
723            
724             MCP4801 => 0x100|$MCP_DAC_RESOLUTION_08,
725             MCP4811 => 0x200|$MCP_DAC_RESOLUTION_10,
726             MCP4821 => 0x300|$MCP_DAC_RESOLUTION_12,
727             MCP4802 => 0x400|$MCP_DAC_RESOLUTION_08|$MCP_DAC_DUAL_CHANNEL,
728             MCP4812 => 0x500|$MCP_DAC_RESOLUTION_10|$MCP_DAC_DUAL_CHANNEL,
729             MCP4822 => 0x600|$MCP_DAC_RESOLUTION_12|$MCP_DAC_DUAL_CHANNEL,
730             MCP4901 => 0x700|$MCP_DAC_RESOLUTION_08|$MCP_DAC_CAN_BUFFER,
731             MCP4911 => 0x800|$MCP_DAC_RESOLUTION_10|$MCP_DAC_CAN_BUFFER,
732             MCP4921 => 0x900|$MCP_DAC_RESOLUTION_12|$MCP_DAC_CAN_BUFFER,
733             MCP4902 => 0xA00|$MCP_DAC_RESOLUTION_08|$MCP_DAC_DUAL_CHANNEL|$MCP_DAC_CAN_BUFFER,
734             MCP4912 => 0xB00|$MCP_DAC_RESOLUTION_10|$MCP_DAC_DUAL_CHANNEL|$MCP_DAC_CAN_BUFFER,
735             MCP4922 => 0xC00|$MCP_DAC_RESOLUTION_12|$MCP_DAC_DUAL_CHANNEL|$MCP_DAC_CAN_BUFFER,
736             },
737            
738             openthings => {
739            
740             OPENTHINGS_MANUFACTURER_ENERGENIE => 0x04,
741             OPENTHINGS_MANUFACTURER_SENTEC => 0x01,
742             OPENTHINGS_MANUFACTURER_HILDERBRAND => 0x02,
743             OPENTHINGS_MANUFACTURER_RASPBERRY => 0x3F,
744            
745             OPENTHINGS_PARAM_ALARM => 0x21,
746             OPENTHINGS_PARAM_DEBUG_OUTPUT => 0x2D,
747             OPENTHINGS_PARAM_IDENTIFY => 0x3F,
748             OPENTHINGS_PARAM_SOURCE_SELECTOR => 0x40,
749             OPENTHINGS_PARAM_WATER_DETECTOR => 0x41,
750             OPENTHINGS_PARAM_GLASS_BREAKAGE => 0x42,
751             OPENTHINGS_PARAM_CLOSURES => 0x43,
752             OPENTHINGS_PARAM_DOOR_BELL => 0x44,
753             OPENTHINGS_PARAM_ENERGY => 0x45,
754             OPENTHINGS_PARAM_FALL_SENSOR => 0x46,
755             OPENTHINGS_PARAM_GAS_VOLUME => 0x47,
756             OPENTHINGS_PARAM_AIR_PRESSURE => 0x48,
757             OPENTHINGS_PARAM_ILLUMINANCE => 0x49,
758             OPENTHINGS_PARAM_LEVEL => 0x4C,
759             OPENTHINGS_PARAM_RAINFALL => 0x4D,
760             OPENTHINGS_PARAM_APPARENT_POWER => 0x50,
761             OPENTHINGS_PARAM_POWER_FACTOR => 0x51,
762             OPENTHINGS_PARAM_REPORT_PERIOD => 0x52,
763             OPENTHINGS_PARAM_SMOKE_DETECTOR => 0x53,
764             OPENTHINGS_PARAM_TIME_AND_DATE => 0x54,
765             OPENTHINGS_PARAM_VIBRATION => 0x56,
766             OPENTHINGS_PARAM_WATER_VOLUME => 0x57,
767             OPENTHINGS_PARAM_WIND_SPEED => 0x58,
768             OPENTHINGS_PARAM_GAS_PRESSURE => 0x61,
769             OPENTHINGS_PARAM_BATTERY_LEVEL => 0x62,
770             OPENTHINGS_PARAM_CO_DETECTOR => 0x63,
771             OPENTHINGS_PARAM_DOOR_SENSOR => 0x64,
772             OPENTHINGS_PARAM_EMERGENCY => 0x65,
773             OPENTHINGS_PARAM_FREQUENCY => 0x66,
774             OPENTHINGS_PARAM_GAS_FLOW_RATE => 0x67,
775             OPENTHINGS_PARAM_RELATIVE_HUMIDITY =>0x68,
776             OPENTHINGS_PARAM_CURRENT => 0x69,
777             OPENTHINGS_PARAM_JOIN => 0x6A,
778             OPENTHINGS_PARAM_LIGHT_LEVEL => 0x6C,
779             OPENTHINGS_PARAM_MOTION_DETECTOR => 0x6D,
780             OPENTHINGS_PARAM_OCCUPANCY => 0x6F,
781             OPENTHINGS_PARAM_REAL_POWER => 0x70,
782             OPENTHINGS_PARAM_REACTIVE_POWER => 0x71,
783             OPENTHINGS_PARAM_ROTATION_SPEED => 0x72,
784             OPENTHINGS_PARAM_SWITCH_STATE => 0x73,
785             OPENTHINGS_PARAM_TEMPERATURE => 0x74,
786             OPENTHINGS_PARAM_VOLTAGE => 0x76,
787             OPENTHINGS_PARAM_WATER_FLOW_RATE => 0x77,
788             OPENTHINGS_PARAM_WATER_PRESSURE => 0x78,
789             OPENTHINGS_PARAM_PHASE_1_POWER => 0x79,
790             OPENTHINGS_PARAM_PHASE_2_POWER => 0x7A,
791             OPENTHINGS_PARAM_PHASE_3_POWER => 0x7B,
792             OPENTHINGS_PARAM_3_PHASE_TOTAL => 0x7C,
793            
794             # from Energenie examples
795             OPENTHINGS_PARAM_TEST => 0xAA,
796             OPENTHINGS_WRITE_MASK => 0x80,
797            
798             OPENTHINGS_UINT => 0x00,
799             OPENTHINGS_UINT_BP4 => 0x10,
800             OPENTHINGS_UINT_BP8 => 0x20,
801             OPENTHINGS_UINT_BP12 => 0x30,
802             OPENTHINGS_UINT_BP16 => 0x40,
803             OPENTHINGS_UINT_BP20 => 0x50,
804             OPENTHINGS_UINT_BP24 => 0x60,
805             OPENTHINGS_CHAR => 0x70,
806             OPENTHINGS_SINT => 0x80,
807             OPENTHINGS_SINT_BP8 => 0x90,
808             OPENTHINGS_SINT_BP16 => 0xA0,
809             OPENTHINGS_SINT_BP24 => 0xB0,
810             OPENTHINGS_ENUMERATION => 0xC0,
811             # D0,E0 RESERVED
812             OPENTHINGS_FLOAT => 0xF0,
813             },
814            
815             energenie => {
816             ENERGENIE_ENER314_DUMMY_GROUP => 0xFFFFFF,
817            
818             ENERGENIE_MANUFACTURER_ID => 0x04,
819            
820             ENERGENIE_PRODUCT_ID_MIHO004 => 0x01,
821             ENERGENIE_PRODUCT_ID_MIHO005 => 0x02,
822             ENERGENIE_PRODUCT_ID_MIHO013 => 0x03,
823             ENERGENIE_PRODUCT_ID_MIHO006 => 0x05,
824            
825             ENERGENIE_PRODUCT_ID_MIHO032 => 0x0C,
826             ENERGENIE_PRODUCT_ID_MIHO033 => 0x0D,
827            
828             ENERGENIE_DEFAULT_CRYPTSEED => 242,
829             ENERGENIE_DEFAULT_CRYPTPIP => 0x0100,
830            
831             ENERGENIE_FIFOTHRESH_FSK => 0x81, # Condition to start packet transmission: at least one byte in FIFO
832             ENERGENIE_FIFOTHRESH_OOK => 0x1E, # Condition to start packet transmission: wait for 30 bytes in FIFO
833             ENERGENIE_TXOOK_REPEAT_RATE => 25,
834             ENERGENIE_MESSAGE_BUF_SIZE => 66,
835             ENERGENIE_MAX_FIFO_SIZE => 66,
836             ENERGENIE_NODEADDRESS01 => 0x01, # Node address used in address filtering
837             ENERGENIE_NODEADDRESS04 => 0x04, # Node address used in address filtering
838             ENERGENIE_FDEVMSB_FSK => 0x01, # frequency deviation 5kHz => 0x0052 -> 30kHz => 0x01EC
839             ENERGENIE_FDEVLSB_FSK => 0xEC, # frequency deviation 5kHz => 0x0052 -> 30kHz => 0x01EC
840             ENERGENIE_FDEVMSB_OOK => 0,
841             ENERGENIE_FDEVLSB_OOK => 0,
842             ENERGENIE_FRMSB_434 => 0x6C, # carrier freq -> 434.3MHz => 0x6C9333
843             ENERGENIE_FRMID_434 => 0x93, # carrier freq -> 434.3MHz => 0x6C9333
844             ENERGENIE_FRLSB_434 => 0x33, # carrier freq -> 434.3MHz => 0x6C9333
845             ENERGENIE_FRMSB_433 => 0x6C, # carrier freq -> 433.92MHz => 0x6C7AE1
846             ENERGENIE_FRMID_433 => 0x7A, # carrier freq -> 433.92MHz => 0x6C7AE1
847             ENERGENIE_FRLSB_433 => 0xE1, # carrier freq -> 433.92MHz => 0x6C7AE1
848             ENERGENIE_SYNCVALUE1_FSK => 0x2D, # 1st byte of Sync word
849             ENERGENIE_SYNCVALUE2_FSK => 0xD4, # 2nd byte of Sync word
850             ENERGENIE_SYNCVALUE1_OOK => 0x80, # 1nd byte of Sync word
851            
852             ENERGENIE_SYNC_SIZE_2 => 0x88, # Size of the Synch word = 2 (SyncSize + 1)
853             ENERGENIE_SYNC_SIZE_4 => 0x98, # Size of the Synch word = 4 (SyncSize + 1)
854            
855             ENERGENIE_PACKETCONFIG1_FSK => 0xA2, # Variable length, Manchester coding, Addr must match NodeAddress
856             ENERGENIE_PACKETCONFIG1_FSK_NOADDR => 0xA0, # Variable length, Manchester coding
857             ENERGENIE_PACKETCONFIG1_OOK => 0, # Fixed length, no Manchester coding
858             ENERGENIE_NODEADDRESS => 0x06, # Node address used in address filtering ( when enabled )
859            
860             ENERGENIE_PAYLOADLEN_OOK => 13 + 8 * 17, # fixed OOK Payload Length
861             },
862            
863             si470n => {
864             SI4701 => 1,
865             SI4702 => 2,
866             SI4703 => 3,
867             },
868            
869             pca9685 => {
870             PCA_9685_SERVOTYPE_DEFAULT => 1,
871             PCA_9685_SERVOTYPE_EXT_1 => 2,
872             PCA_9685_SERVOTYPE_EXT_2 => 3,
873             PCA_9685_SERVOTYPE_SG90 => 4,
874            
875             PCA_9685_SERVO_CHANNEL_MASK => 0x0FFF,
876             PCA_9685_FULL_MASK => 0x1000,
877            
878             PCA_9685_SERVO_DIRECTION_CW => 1,
879             PCA_9685_SERVO_DIRECTION_AC => 2,
880             },
881            
882             oled => {
883             SSD1306_128_X_64_I2C => 0x01 + 0x04 + 0x08 + 0x20,
884             SSD1306_128_X_32_I2C => 0x01 + 0x04 + 0x10 + 0x20,
885            
886             SH1106_128_X_64_I2C => 0x02 + 0x04 + 0x08 + 0x20,
887             SH1106_128_X_32_I2C => 0x02 + 0x04 + 0x10 + 0x20,
888            
889             SSD1306_128_X_64_SPI => 0x01 + 0x04 + 0x08 + 0x40,
890             SSD1306_128_X_32_SPI => 0x01 + 0x04 + 0x10 + 0x40,
891            
892             SH1106_128_X_64_SPI => 0x02 + 0x04 + 0x08 + 0x40,
893             SH1106_128_X_32_SPI => 0x02 + 0x04 + 0x10 + 0x40,
894             },
895            
896             ms5611 => {
897             MS5611_OSR_256 => 0x00, # // ADC OSR=256
898             MS5611_OSR_512 => 0x02, # // ADC OSR=512
899             MS5611_OSR_1024 => 0x04, # // ADC OSR=1024
900             MS5611_OSR_2048 => 0x06, # // ADC OSR=2048
901             MS5611_OSR_4096 => 0x08, # // ADC OSR=4096
902             },
903            
904             tmp102 => {
905             TMP102_CR_0_25HZ => 0,
906             TMP102_CR_1HZ => 1,
907             TMP102_CR_4HZ => 2,
908             TMP102_CR_8HZ => 3,
909            
910             TMP102_FAULTS_1 => 0,
911             TMP102_FAULTS_2 => 1,
912             TMP102_FAULTS_4 => 2,
913             TMP102_FAULTS_6 => 3,
914             },
915            
916             epaper => {
917             EPD_WS_1_54_200_X_200_A => 0x01,
918             EPD_WS_1_54_200_X_200_B => 0x02,
919             EPD_WS_1_54_152_X_152_C => 0x03,
920             EPD_WS_2_13_250_X_122_A => 0x04,
921             EPD_WS_2_13_212_X_104_B => 0x05,
922             EPD_WS_2_90_296_X_128_A => 0x06,
923             EPD_WS_2_90_296_X_128_B => 0x07,
924            
925             EPD_PIMORONI_INKY_PHAT_V2 => 0x80,
926            
927             EPD_ROTATION_0 => 0,
928             EPD_ROTATION_90 => 90,
929             EPD_ROTATION_180 => 180,
930             EPD_ROTATION_270 => 270,
931            
932             EPD_FRAME_BPP_1 => 0x01,
933             EPD_FRAME_BPP_2 => 0x02,
934             EPD_FRAME_TYPE_BLACK => 0x01,
935             EPD_FRAME_TYPE_COLOUR => 0x02,
936             EPD_FRAME_TYPE_COLOR => 0x02,
937             EPD_FRAME_TYPE_WHITE => 0x03,
938             EPD_FRAME_TYPE_UNUSED => 0x04,
939            
940             EPD_BLACK_PEN => 0x01,
941             EPD_COLOUR_PEN => 0x02,
942             EPD_COLOR_PEN => 0x02,
943             EPD_RED_PEN => 0x02,
944             EPD_YELLOW_PEN => 0x02,
945            
946             EPD_UPD_MODE_FIXED => 0x01,
947             EPD_UPD_MODE_FULL => 0x02,
948             EPD_UPD_MODE_PARTIAL => 0x03,
949            
950             EPD_BORDER_FLOAT => 0x00,
951             EPD_BORDER_WHITE => 0x01,
952             EPD_BORDER_BLACK => 0x02,
953             EPD_BORDER_COLOUR => 0x03,
954             EPD_BORDER_COLOR => 0x03,
955             EPD_BORDER_RED => 0x03,
956             EPD_BORDER_YELLOW => 0x03,
957            
958             EPD_BORDER_POR => 0xFF,
959             },
960            
961             fl3730 => {
962             # CONFIGURATION REG 0x00
963             FL3730_SSD_NORMAL => 0b00000000,
964             FL3730_SSD_SHUTDOWN => 0b10000000,
965            
966             FL3730_DM_MATRIX_1 => 0b00000,
967             FL3730_DM_MATRIX_2 => 0b01000,
968             FL3730_DM_MATRIX_BOTH => 0b11000,
969            
970             FL3730_AEN_OFF => 0b000,
971             FL3730_AEN_ON => 0b100,
972            
973             FL3730_ADM_8X8 => 0b00,
974             FL3730_ADM_7X9 => 0b01,
975             FL3730_ADM_6X10 => 0b10,
976             FL3730_ADM_5X11 => 0b11,
977            
978             # LIGHTING EFFECT REG 0x0D
979             FL3730_AGS_0_DB => 0b0000000,
980             FL3730_AGS_3_DB => 0b0010000,
981             FL3730_AGS_6_DB => 0b0100000,
982             FL3730_AGS_9_DB => 0b0110000,
983             FL3730_AGS_12_DB => 0b1000000,
984             FL3730_AGS_15_DB => 0b1010000,
985             FL3730_AGS_18_DB => 0b1100000,
986             FL3730_AGS_M6_DB => 0b1110000,
987            
988             FL3730_CS_05_MA => 0b1000,
989             FL3730_CS_10_MA => 0b1001,
990             FL3730_CS_15_MA => 0b1010,
991             FL3730_CS_20_MA => 0b1011,
992             FL3730_CS_25_MA => 0b1100,
993             FL3730_CS_30_MA => 0b1101,
994             FL3730_CS_35_MA => 0b1110,
995             FL3730_CS_40_MA => 0b0000,
996             FL3730_CS_45_MA => 0b0001,
997             FL3730_CS_50_MA => 0b0010,
998             FL3730_CS_55_MA => 0b0011,
999             FL3730_CS_60_MA => 0b0100,
1000             FL3730_CS_65_MA => 0b0101,
1001             FL3730_CS_70_MA => 0b0110,
1002             FL3730_CS_75_MA => 0b0111,
1003             },
1004            
1005             max7219 => {
1006             MAX7219_FLAG_FLIPPED => 0x01,
1007             MAX7219_FLAG_MIRROR => 0x02,
1008             MAX7219_FLAG_DECIMAL => 0x04,
1009            
1010             MAX7219_REG_NOOP => 0x00,
1011             MAX7219_REG_DIGIT_0 => 0x01,
1012             MAX7219_REG_DIGIT_1 => 0x02,
1013             MAX7219_REG_DIGIT_2 => 0x03,
1014             MAX7219_REG_DIGIT_3 => 0x04,
1015             MAX7219_REG_DIGIT_4 => 0x05,
1016             MAX7219_REG_DIGIT_5 => 0x06,
1017             MAX7219_REG_DIGIT_6 => 0x07,
1018             MAX7219_REG_DIGIT_7 => 0x08,
1019             MAX7219_REG_DECODE_MODE => 0x09,
1020             MAX7219_REG_INTENSITY => 0x0A,
1021             MAX7219_REG_SCAN_LIMIT => 0x0B,
1022             MAX7219_REG_SHUTDOWN => 0x0C,
1023             MAX7219_REG_TEST => 0x0F,
1024             },
1025            
1026             hilink => {
1027             HILINK_CONNSTATUS_CONNECTING => 900,
1028             HILINK_CONNSTATUS_CONNECTED => 901,
1029             HILINK_CONNSTATUS_DISCONNECTED => 902,
1030             HILINK_CONNSTATUS_DISCONNECTING => 903,
1031             },
1032            
1033             mfrc522 => {
1034             ## MIFARE STATUS CODES
1035             MFRC522_STATUS_OK => 1, #// Success
1036             MFRC522_STATUS_ERROR => 2, #// Error in communication
1037             MFRC522_STATUS_COLLISION => 3, #// Collission detected
1038             MFRC522_STATUS_TIMEOUT => 4, #// Timeout in communication.
1039             MFRC522_STATUS_NO_ROOM => 5, #// A buffer is not big enough.
1040             MFRC522_STATUS_INTERNAL_ERROR => 6, #// Internal error in the code. Should not happen ;-)
1041             MFRC522_STATUS_INVALID => 7, #// Invalid argument.
1042             MFRC522_STATUS_CRC_WRONG => 8, #// The CRC_A does not match
1043            
1044             MFRC522_STATUS_UNSUPPORTED_TYPE => 9,
1045             MFRC522_STATUS_BLOCK_NOT_ALLOWED => 10,
1046             MFRC522_STATUS_BAD_PARAM => 11,
1047            
1048             MFRC522_STATUS_MIFARE_NACK => 0xff, #// A MIFARE PICC responded with NAK.
1049            
1050             ## MF522 MFRC522 error codes.
1051             MFRC522_ERROR_OK => 0, # Everything A-OK.
1052             MFRC522_ERROR_NOTAGERR => 1, # No tag error
1053             MFRC522_ERROR_ERR => 2, # General error
1054              
1055             # MF522 Command word
1056             MFRC522_IDLE => 0x00, # NO action; Cancel the current command
1057             MFRC522_MEM => 0x01, # Store 25 byte into the internal buffer.
1058             MFRC522_GENID => 0x02, # Generates a 10 byte random ID number.
1059             MFRC522_CALCCRC => 0x03, # CRC Calculate or selftest.
1060             MFRC522_TRANSMIT => 0x04, # Transmit data
1061             MFRC522_NOCMDCH => 0x07, # No command change.
1062             MFRC522_RECEIVE => 0x08, # Receive Data
1063             MFRC522_TRANSCEIVE => 0x0C, # Transmit and receive data,
1064             MFRC522_AUTHENT => 0x0E, # Authentication Key
1065             MFRC522_SOFTRESET => 0x0F, # Reset
1066              
1067             # Mifare_One tag command word
1068             MIFARE_REQIDL => 0x26, # find the antenna area does not enter hibernation
1069             MIFARE_REQALL => 0x52, # find all the tags antenna area
1070             MIFARE_ANTICOLL => 0x88, # anti-collision
1071             MIFARE_CASCADE => 0x88, # cascade tag
1072             MIFARE_SELECTTAG => 0x93, # selection tag
1073             MIFARE_SELECT_CL1 => 0x93,
1074             MIFARE_SELECT_CL2 => 0x95,
1075             MIFARE_SELECT_CL3 => 0x97,
1076             MIFARE_AUTHENT1A => 0x60, # authentication key A
1077             MIFARE_AUTHENT1B => 0x61, # authentication key B
1078             MIFARE_READ => 0x30, # Read Block
1079             MIFARE_WRITE => 0xA0, # write block
1080             MIFARE_DECREMENT => 0xC0, # debit
1081             MIFARE_INCREMENT => 0xC1, # recharge
1082             MIFARE_RESTORE => 0xC2, # transfer block data to the buffer
1083             MIFARE_TRANSFER => 0xB0, # save the data in the buffer
1084             MIFARE_HALT => 0x50, # Sleep
1085              
1086              
1087             #------------------ MFRC522 registers---------------
1088             #Page 0:Command and Status
1089             MFRC522_REG_Reserved00 => 0x00,
1090             MFRC522_REG_CommandReg => 0x01,
1091             MFRC522_REG_CommIEnReg => 0x02,
1092             MFRC522_REG_DivIEnReg => 0x03,
1093             MFRC522_REG_CommIrqReg => 0x04,
1094             MFRC522_REG_DivIrqReg => 0x05,
1095             MFRC522_REG_ErrorReg => 0x06,
1096             MFRC522_REG_Status1Reg => 0x07,
1097             MFRC522_REG_Status2Reg => 0x08,
1098             MFRC522_REG_FIFODataReg => 0x09,
1099             MFRC522_REG_FIFOLevelReg => 0x0A,
1100             MFRC522_REG_WaterLevelReg => 0x0B,
1101             MFRC522_REG_ControlReg => 0x0C,
1102             MFRC522_REG_BitFramingReg => 0x0D,
1103             MFRC522_REG_CollReg => 0x0E,
1104             MFRC522_REG_Reserved01 => 0x0F,
1105             #Page 1:Command
1106             MFRC522_REG_Reserved10 => 0x10,
1107             MFRC522_REG_ModeReg => 0x11,
1108             MFRC522_REG_TxModeReg => 0x12,
1109             MFRC522_REG_RxModeReg => 0x13,
1110             MFRC522_REG_TxControlReg => 0x14,
1111             MFRC522_REG_TxAutoReg => 0x15,
1112             MFRC522_REG_TxSelReg => 0x16,
1113             MFRC522_REG_RxSelReg => 0x17,
1114             MFRC522_REG_RxThresholdReg => 0x18,
1115             MFRC522_REG_DemodReg => 0x19,
1116             MFRC522_REG_Reserved11 => 0x1A,
1117             MFRC522_REG_Reserved12 => 0x1B,
1118             MFRC522_REG_MifareReg => 0x1C,
1119             MFRC522_REG_Reserved13 => 0x1D,
1120             MFRC522_REG_Reserved14 => 0x1E,
1121             MFRC522_REG_SerialSpeedReg => 0x1F,
1122             #Page 2:CFG
1123             MFRC522_REG_Reserved20 => 0x20,
1124             MFRC522_REG_CRCResultRegM => 0x21,
1125             MFRC522_REG_CRCResultRegH => 0x21,
1126             MFRC522_REG_CRCResultRegL => 0x22,
1127             MFRC522_REG_Reserved21 => 0x23,
1128             MFRC522_REG_ModWidthReg => 0x24,
1129             MFRC522_REG_Reserved22 => 0x25,
1130             MFRC522_REG_RFCfgReg => 0x26,
1131             MFRC522_REG_GsNReg => 0x27,
1132             MFRC522_REG_CWGsPReg => 0x28,
1133             MFRC522_REG_ModGsPReg => 0x29,
1134             MFRC522_REG_TModeReg => 0x2A,
1135             MFRC522_REG_TPrescalerReg => 0x2B,
1136             MFRC522_REG_TReloadRegH => 0x2C,
1137             MFRC522_REG_TReloadRegL => 0x2D,
1138             MFRC522_REG_TCounterValueRegH => 0x2E,
1139             MFRC522_REG_TCounterValueRegL => 0x2F,
1140             #Page 3:TestRegister
1141             MFRC522_REG_Reserved30 => 0x30,
1142             MFRC522_REG_TestSel1Reg => 0x31,
1143             MFRC522_REG_TestSel2Reg => 0x32,
1144             MFRC522_REG_TestPinEnReg => 0x33,
1145             MFRC522_REG_TestPinValueReg => 0x34,
1146             MFRC522_REG_TestBusReg => 0x35,
1147             MFRC522_REG_AutoTestReg => 0x36,
1148             MFRC522_REG_VersionReg => 0x37,
1149             MFRC522_REG_AnalogTestReg => 0x38,
1150             MFRC522_REG_TestDAC1Reg => 0x39,
1151             MFRC522_REG_TestDAC2Reg => 0x3A,
1152             MFRC522_REG_TestADCReg => 0x3B,
1153             MFRC522_REG_Reserved31 => 0x3C,
1154             MFRC522_REG_Reserved32 => 0x3D,
1155             MFRC522_REG_Reserved33 => 0x3E,
1156             MFRC522_REG_Reserved34 => 0x3F,
1157            
1158             MFRC522_PICC_TYPE_UNKNOWN => 0,
1159             MFRC522_PICC_TYPE_ISO_14443_4 => 1, #// PICC compliant with ISO/IEC 14443-4
1160             MFRC522_PICC_TYPE_ISO_18092 => 2, #// PICC compliant with ISO/IEC 18092 (NFC)
1161             MFRC522_PICC_TYPE_MIFARE_MINI => 3, #// MIFARE Classic protocol, 320 bytes
1162             MFRC522_PICC_TYPE_MIFARE_1K => 4, #// MIFARE Classic protocol, 1KB
1163             MFRC522_PICC_TYPE_MIFARE_4K => 5, #// MIFARE Classic protocol, 4KB
1164             MFRC522_PICC_TYPE_MIFARE_UL => 6, #// MIFARE Ultralight or Ultralight C
1165             MFRC522_PICC_TYPE_MIFARE_PLUS => 7, #// MIFARE Plus
1166             MFRC522_PICC_TYPE_MIFARE_DESFIRE => 8, #// MIFARE DESFire
1167             MFRC522_PICC_TYPE_TNP3XXX => 9, #// Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
1168             MFRC522_PICC_TYPE_NOT_COMPLETE => 0xff, #// SAK indicates UID is not complete.
1169            
1170             MIFARE_MF_ACK => 0xA, #// The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
1171             MIFARE_MF_KEY_SIZE => 6, #// A Mifare Crypto1 key is 6 bytes.
1172            
1173             MFCR522_RXGAIN_18dB => 0x00 << 4, # // 000b - 18 dB, minimum
1174             MFCR522_RXGAIN_23dB => 0x01 << 4, # // 001b - 23 dB
1175             MFCR522_RXGAIN_18dB_2 => 0x02 << 4, # // 010b - 18 dB, it seems 010b is a duplicate for 000b
1176             MFCR522_RXGAIN_23dB_2 => 0x03 << 4, # // 011b - 23 dB, it seems 011b is a duplicate for 001b
1177             MFCR522_RXGAIN_33dB => 0x04 << 4, # // 100b - 33 dB, average, and typical default
1178             MFCR522_RXGAIN_38dB => 0x05 << 4, # // 101b - 38 dB
1179             MFCR522_RXGAIN_43dB => 0x06 << 4, # // 110b - 43 dB
1180             MFCR522_RXGAIN_48dB => 0x07 << 4, # // 111b - 48 dB, maximum
1181             MFCR522_RXGAIN_MIN => 0x00 << 4, # // 000b - 18 dB, minimum, convenience for MFCR522_RXGAIN_18dB
1182             MFCR522_RXGAIN_AVG => 0x04 << 4, # // 100b - 33 dB, average, convenience for MFCR522_RXGAIN_33dB
1183             MFCR522_RXGAIN_MAX => 0x07 << 4 # // 111b - 48 dB, maximum, convenience for MFCR522_RXGAIN_48dB
1184            
1185             },
1186             };
1187              
1188             my $tagaliases = {
1189             mcp23x17 => [ qw( mcp23017 mcp23S17 ) ],
1190             rpi => [ qw( raspberry ) ],
1191             fl3730 => [ qw( is31fl3730 )]
1192             };
1193              
1194             sub hipi_export_ok {
1195 5     5 0 15 my @names = ();
1196 5         42 for my $tag ( keys %$const ) {
1197 105         110 for my $cname ( keys %{$const->{$tag}} ) {
  105         709  
1198 4775         5414 push @names, $cname;
1199             }
1200             }
1201 5         652 return @names;
1202             }
1203              
1204             sub hipi_export_constants {
1205 5     5 0 11 my $constants = {};
1206 5         30 for my $tag ( keys %$const ) {
1207 105         103 for my $cname ( keys %{$const->{$tag}} ) {
  105         773  
1208 4775         6631 $constants->{$cname} = $const->{$tag}->{$cname};
1209             }
1210             }
1211 5         27993 return $constants;
1212             }
1213              
1214             sub hipi_export_tags {
1215 5     5 0 15 my %tags = ();
1216 5         26 for my $tag ( keys %$const ) {
1217 105         116 my @names = ();
1218 105         108 for my $cname ( keys %{$const->{$tag}} ) {
  105         524  
1219 4775         5191 push @names, $cname;
1220             }
1221 105         342 $tags{$tag} = \@names;
1222 105 100       198 if(exists($tagaliases->{$tag})) {
1223 15         20 for my $alias ( @{ $tagaliases->{$tag} } ) {
  15         28  
1224 20         79 $tags{$alias} = \@names;
1225             }
1226             }
1227             }
1228 5         81 return %tags;
1229             }
1230              
1231             1;
1232              
1233             __END__