File Coverage

blib/lib/CPU/x86_64/InstructionWriter.pm

Criterion	Covered	Total	%
statement	823	1010	81.4
branch	282	404	69.8
condition	98	258	37.9
subroutine	431	551	78.2
pod	102	464	21.9
total	1736	2687	64.6

package CPU::x86_64::InstructionWriter;
our $VERSION = '0.001'; # VERSION
use v5.10;
use Moo 2;
use Carp;
use Scalar::Util 'looks_like_number';
use Exporter 'import';
use CPU::x86_64::InstructionWriter::Unknown;
use CPU::x86_64::InstructionWriter::Label;

# ABSTRACT: Assemble x86-64 instructions using a pure-perl API


(0x7FFFFFFE << 31) > 0 && (0x7FFFFFFE << 63) == 0
	or die "Author is lazy and requires 64-bit perl integers\n";
no warnings 'portable';

my @byte_registers= qw( AH AL BH BL CH CL DH DL SPL BPL SIL DIL R8B R9B R10B R11B R12B R13B R14B R15B );
my %byte_register_alias= ( map {; "R${_}L" => "R${_}B" } 8..15 );
my @word_registers= qw( AX BX CX DX SI DI SP BP R8W R9W R10W R11W R12W R13W R14W R15W );
my @long_registers= qw( EAX EBX ECX EDX ESI EDI ESP EBP R8D R9D R10D R11D R12D R13D R14D R15D );
my @quad_registers= qw( RAX RBX RCX RDX RSI RDI RSP RBP R8 R9 R10 R11 R12 R13 R14 R15 RIP RFLAGS );
my @registers= ( @byte_registers, @word_registers, @long_registers, @quad_registers );
{
	# Create a constant for each register name
	no strict 'refs';
	eval 'sub '.$_.' { \''.$_.'\' } 1' || croak $@
		for @registers;
	*{__PACKAGE__."::$_"}= *{__PACKAGE__."::$byte_register_alias{$_}"}
		for keys %byte_register_alias;
}

# Map 64-bit register names to the numeric register number
my %regnum64= (
	RAX => 0, RCX => 1, RDX => 2, RBX => 3,
	rax => 0, rcx => 1, rdx => 2, rbx => 3,
	RSP => 4, RBP => 5, RSI => 6, RDI => 7,
	rsp => 4, rbp => 5, rsi => 6, rdi => 7,
	map { $_ => $_, "R$_" => $_, "r$_" => $_ } 0..15
);

my %regnum32= (
	EAX => 0, ECX => 1, EDX => 2, EBX => 3,
	eax => 0, ecx => 1, edx => 2, ebx => 3,
	ESP => 4, EBP => 5, ESI => 6, EDI => 7,
	esp => 4, ebp => 5, esi => 6, edi => 7,
	map { $_ => $_, "R${_}D" => $_, "r${_}d" => $_ } 0..15
);

my %regnum16= (
	AX => 0, CX => 1, DX => 2, BX => 3,
	ax => 0, cx => 1, dx => 2, bx => 3,
	SP => 4, BP => 5, SI => 6, DI => 7,
	sp => 4, bp => 5, si => 6, di => 7,
	map { $_ => $_, "R${_}W" => $_, "r${_}w" => $_ } 0..15
);

my %regnum8= (
	AL => 0, CL => 1, DL => 2, BL => 3,
	al => 0, cl => 1, dl => 2, bl => 3,
	SPL => 4, BPL => 5, SIL => 6, DIL => 7,
	spl => 4, bpl => 5, sil => 6, dil => 7,
	map { $_ => $_, "R${_}B" => $_, "r${_}b" => $_, "R${_}L" => $_, "r${_}l" => $_ } 0..15
);
my %regnum8_high= (
	AH => 4, CH => 5, DH => 6, BH => 7,
	ah => 4, ch => 5, dh => 6, bh => 7,
);
my %register_bits= (
	(map { $_ => 64 } keys %regnum64),
	(map { $_ => 32 } keys %regnum32),
	(map { $_ => 16 } keys %regnum16),
	(map { $_ =>  8 } keys %regnum8),
);

sub unknown   { CPU::x86_64::InstructionWriter::Unknown->new(name => $_[0]); }
sub unknown8  { CPU::x86_64::InstructionWriter::Unknown->new(bits =>  8, name => $_[0]); }
sub unknown16 { CPU::x86_64::InstructionWriter::Unknown->new(bits => 16, name => $_[0]); }
sub unknown32 { CPU::x86_64::InstructionWriter::Unknown->new(bits => 32, name => $_[0]); }
sub unknown64 { CPU::x86_64::InstructionWriter::Unknown->new(bits => 64, name => $_[0]); }
sub unknown7  { CPU::x86_64::InstructionWriter::Unknown->new(bits =>  7, name => $_[0]); }
sub unknown15 { CPU::x86_64::InstructionWriter::Unknown->new(bits => 15, name => $_[0]); }
sub unknown31 { CPU::x86_64::InstructionWriter::Unknown->new(bits => 31, name => $_[0]); }
sub unknown63 { CPU::x86_64::InstructionWriter::Unknown->new(bits => 63, name => $_[0]); }

our %EXPORT_TAGS= (
	registers    => \@registers,
	unknown      => [qw( unknown unknown8 unknown16 unknown32 unknown64 unknown7 unknown15 unknown31 unknown63 )],
);
our @EXPORT_OK= ( map { @{$_} } values %EXPORT_TAGS );


has start_address         => ( is => 'rw', default => sub { unknown64() } );
has debug                 => ( is => 'rw' );

has _buf                  => ( is => 'rw', default => sub { '' } );
has _unresolved           => ( is => 'rw', default => sub { [] } );


has labels                => ( is => 'rw', default => sub {; {} } );


sub get_label {
	my ($self, $name)= @_;
	my $labels= $self->labels;
	unless (defined $name && defined $labels->{$name}) {
		my $label= bless { relative_to => $self->start_address }, __PACKAGE__.'::Label';
		$name= "$label" unless defined $name;
		$label->{name}= $name;
		$labels->{$name}= $label;
	}
	$labels->{$name};
}


sub label {
	@_ == 2 or croak "Invalid arguments to 'mark'";

	# If they gave an undefined label, we auto-populate it, which modifies
	# the variable they passed to this function.
	$_[1]= $_[0]->get_label
		unless defined $_[1];

	my ($self, $label)= @_;
	# If they give a label by name, auto-inflate it
	$label= $self->get_label($label)
		unless ref $label;

	# A label can only exist once
	defined $label->{offset} and croak "Can't mark label '$label->{name}' twice";

	# Set the label's current location
	$label->{offset}= length($self->{_buf});
	$label->{len}= 0;

	# Add it to the list of unresolved things, so its position can be updated
	push @{ $self->_unresolved }, $label;
	return $self;
}


sub bytes {
	my $self= shift;
	$self->_resolve;
	return $self->_buf;
}


sub data     { $_[0]{_buf} .= $_[1] }
sub data_i8  { $_[0]{_buf} .= chr($_[1]) }
sub data_i16 { $_[0]{_buf} .= pack('v', $_[1]) }
sub data_i32 { $_[0]{_buf} .= pack('V', $_[1]) }
sub data_i64 { $_[0]{_buf} .= pack('


sub data_f32 { $_[0]{_buf} .= pack('f', $_[1]) }
sub data_f64 { $_[0]{_buf} .= pack('d', $_[1]) }


sub align { # ( self, bytes, fill_byte)
	my ($self, $bytes, $fill)= @_;
	($bytes & ($bytes-1))
		and croak "Bytes must be a power of 2";
	$self->_align(~($bytes-1), $fill);
}
sub _align {
	my ($self, $mask, $fill)= @_;
	$fill //= "\x90";
	length($fill) == 1 or croak "Fill byte must be 1 byte long";
	$self->_mark_unresolved(
		0,
		encode => sub {
			#warn "start=$_[1]{start}, mask=$mask, ~mask=${\~$mask} ".((($_[1]{start} + ~$mask) & $mask) - $_[1]{start})."\n";
			$fill x ((($_[1]{offset} + ~$mask) & $mask) - $_[1]{offset})
		}
	);
}
sub align2 { splice @_, 1, 0, ~1; &_align; }
sub align4 { splice @_, 1, 0, ~3; &_align; }
sub align8 { splice @_, 1, 0, ~7; &_align; }


sub _autodetect_signature_dst_src {
	my ($self, $opname, $dst, $src, $bits)= @_;
	$bits ||= $register_bits{$dst} || $register_bits{$src}
		or croak "Can't determine bit-width of ".uc($opname)." instruction. "
		        ."Use ->$opname(\$dst, \$src, \$bits) to clarify, when there is no register";
	my $dst_type= looks_like_number($dst)? 'imm'
	            : ref $dst eq 'ARRAY'? 'mem'
	            : ref $dst && ref($dst)->can('value')? 'imm'
	            : $register_bits{$dst}? 'reg'
	            : croak "Can't identify type of destination operand $dst";
	my $src_type= looks_like_number($src)? 'imm'
	            : ref $src eq 'ARRAY'? 'mem'
	            : ref $src && ref($src)->can('value')? 'imm'
	            : $register_bits{$src}? 'reg'
	            : croak "Can't identify type of source operand $src";
	my $method= "$opname${bits}_${dst_type}_${src_type}";
	($self->can($method) || croak "No ".uc($opname)." variant $method available")
		->($self, $dst, $src);
}

sub _autodetect_signature_1op {
	my ($self, $opname, $operand, $bits)= @_;
	my $opr_type= $register_bits{$operand};
	$bits ||= $opr_type
		or croak "Can't determine bit-width of ".uc($opname)." instruction. "
		        ."Use ->$opname(\$arg, \$bits) to clarify, when \$arg is not a register";
	$opr_type= $opr_type? 'reg'
	         : ref $operand eq 'ARRAY'? 'mem'
	         : looks_like_number($operand)? 'imm'
	         : croak "Can't identify type of operand $operand";
	my $method= "$opname${bits}_${opr_type}";
	($self->can($method) || croak "No ".uc($opname)." variant $method available")
		->($self, $operand);
}


sub nop {
	$_[0]{_buf} .= (defined $_[1]? "\x90" x $_[1] : "\x90");
	$_[0];
}

sub pause {
	$_[0]{_buf} .= (defined $_[1]? "\xF3\x90" x $_[1] : "\xF3\x90");
	$_[0]
}


sub call_label {
	@_ == 2 or croak "Wrong arguments";
	$_[1]= $_[0]->get_label
		unless defined $_[1];
	my ($self, $label)= @_;
	use integer;
	$label= $self->get_label($label)
		unless ref $label;
	$self->_mark_unresolved(
		5, # estimated length
		encode => sub {
			my ($self, $params)= @_;
			defined $label->{offset} or croak "Label $label is not marked";
			my $ofs= $label->{offset} - ($params->{offset}+$params->{len});
			($ofs >> 31) == ($ofs >> 32) or croak "Offset must be within 31 bits";
			return pack('CV', 0xE8, $ofs);
		}
	);
	$self;
}

sub call_rel {
	my ($self, $immed)= @_;
	$self->{_buf} .= pack('CV', 0xE8, ref $immed? 0 : $immed);
	$self->_mark_unresolved(-4, encode => '_repack', bits => 32, value => $immed)
		if ref $immed;
	$self;
}

sub call_abs_reg {
	my ($self, $reg)= @_;
	$self->{_buf} .= $self->_encode_op_reg_reg(0, 0xFF, 2,
		$regnum64{$reg} // croak("$reg is not a 64-bit register"),
	);
	$self;
}

sub call_abs_mem { $_[0]->_append_op64_reg_mem(0, 0xFF, 2, $_[1]) }


sub ret {
	my ($self, $pop_bytes)= @_;
	if ($pop_bytes) {
		$self->{_buf} .= pack('Cv', 0xC2, ref $pop_bytes? 0 : $pop_bytes);
		$self->_mark_unresolved(-2, encode => '_repack', bits => 16, value => $pop_bytes)
			if ref $pop_bytes;
	}
	else {
		$self->{_buf} .= "\xC3";
	}
	$self;
}


sub jmp {
	@_ == 2 or croak "Wrong arguments";
	$_[1]= $_[0]->get_label
		unless defined $_[1];
	my ($self, $label)= @_;
	use integer;
	$label= $self->get_label($label)
		unless ref $label;
	$self->_mark_unresolved(
		2, # estimated length
		encode => sub {
			my ($self, $params)= @_;
			defined $label->{offset} or croak "Label $label is not marked";
			my $ofs= $label->{offset} - ($params->{offset}+$params->{len});
			my $short= (($ofs>>7) == ($ofs>>8));
			return $short?
				pack('Cc', 0xEB, $ofs)
				: pack('CV', 0xE9, $ofs);
		}
	);
	$self;
}


sub jmp_abs_reg {
	my ($self, $reg)= @_;
	$self->{_buf} .= $self->_encode_op_reg_reg(0, 0xFF, 4,
		$regnum64{$reg} // croak("$reg is not a 64-bit register"),
	);
	$self;
}


sub jmp_abs_mem {
	$_[0]->_append_op64_reg_mem(0, 0xFF, 4, $_[1]);
}


sub jmp_if_eq { shift->_append_jmp_cond(4, shift) }
*jz= *jmp_if_eq;
*je= *jmp_if_eq;

sub jmp_if_ne { shift->_append_jmp_cond(5, shift) }
*jne= *jmp_if_ne;
*jnz= *jmp_if_ne;


sub jmp_if_unsigned_lt { shift->_append_jmp_cond(2, shift) }
*jb= *jmp_if_unsigned_lt;
*jc= *jmp_if_unsigned_lt;

sub jmp_if_unsigned_gt { shift->_append_jmp_cond(7, shift) }
*ja= *jmp_if_unsigned_gt;

sub jmp_if_unsigned_le { shift->_append_jmp_cond(6, shift) }
*jbe= *jmp_if_unsigned_le;

sub jmp_if_unsigned_ge { shift->_append_jmp_cond(3, shift) }
*jae= *jmp_if_unsigned_ge;
*jnc= *jmp_if_unsigned_ge;


sub jmp_if_signed_lt { shift->_append_jmp_cond(12, shift) }
*jl= *jmp_if_signed_lt;

sub jmp_if_signed_gt { shift->_append_jmp_cond(15, shift) }
*jg= *jmp_if_signed_gt;

sub jmp_if_signed_le { shift->_append_jmp_cond(14, shift) }
*jle= *jmp_if_signed_le;

sub jmp_if_signed_ge { shift->_append_jmp_cond(13, shift) }
*jge= *jmp_if_signed_ge;


sub jmp_if_sign         { shift->_append_jmp_cond(8, shift) }
*js= *jmp_if_sign;

sub jmp_unless_sign     { shift->_append_jmp_cond(9, shift) }
*jns= *jmp_unless_sign;

sub jmp_if_overflow     { shift->_append_jmp_cond(0, shift) }
*jo= *jmp_if_overflow;

sub jmp_unless_overflow { shift->_append_jmp_cond(1, shift) }
*jno= *jmp_unless_overflow;

sub jmp_if_parity_even  { shift->_append_jmp_cond(10, shift) }
*jpe= *jmp_if_parity_even;
*jp= *jmp_if_parity_even;

sub jmp_if_parity_odd   { shift->_append_jmp_cond(11, shift) }
*jpo= *jmp_if_parity_odd;
*jnp= *jmp_if_parity_odd;


sub jmp_cx_zero { shift->_append_jmp_cx(0xE3, shift) }
*jrcxz= *jmp_cx_zero;

sub loop        { shift->_append_jmp_cx(0xE2, shift) }

sub loopz       { shift->_append_jmp_cx(0xE1, shift) }
*loope= *loopz;

sub loopnz      { shift->_append_jmp_cx(0xE0, shift) }
*loopne= *loopnz;


sub mov { splice(@_,1,0,'mov'); &_autodetect_signature_dst_src }


sub mov64_reg_reg { shift->_append_op64_reg_reg(0x89, $_[1], $_[0]) }
sub mov32_reg_reg { shift->_append_op32_reg_reg(0x89, $_[1], $_[0]) }
sub mov16_reg_reg { shift->_append_op16_reg_reg(0x89, $_[1], $_[0]) }
sub mov8_reg_reg  { shift->_append_op8_reg_reg (0x89, $_[1], $_[0]) }


sub mov64_mem_reg { $_[0]->_append_mov_reg_mem($_[2], $_[1], 64, 0x89, 0xA3); }
sub mov64_reg_mem { $_[0]->_append_mov_reg_mem($_[1], $_[2], 64, 0x8B, 0xA1); }
sub mov32_mem_reg { $_[0]->_append_mov_reg_mem($_[2], $_[1], 32, 0x89, 0xA3); }
sub mov32_reg_mem { $_[0]->_append_mov_reg_mem($_[1], $_[2], 32, 0x8B, 0xA1); }
sub mov16_mem_reg { $_[0]->_append_mov_reg_mem($_[2], $_[1], 16, 0x89, 0xA3); }
sub mov16_reg_mem { $_[0]->_append_mov_reg_mem($_[1], $_[2], 16, 0x8B, 0xA1); }
sub mov8_mem_reg  { $_[0]->_append_mov_reg_mem($_[2], $_[1],  8, 0x88, 0xA2); }
sub mov8_reg_mem  { $_[0]->_append_mov_reg_mem($_[1], $_[2],  8, 0x8A, 0xA0); }

sub _append_mov_reg_mem {
	my ($self, $reg, $mem, $bits, $opcode, $ax_opcode)= @_;
	# AX is allowed to load/store 64-bit addresses, if the address is a single constant
	if (!defined $mem->[0] && $mem->[1] && !defined $mem->[2] && ($mem->[1] > 0x7FFFFFFF || ref $mem->[1])) {
		my $disp= $mem->[1];
		if (lc($reg) eq ($bits == 64? 'rax' : $bits == 32? 'eax' : $bits == 16? 'ax' : 'al')) {
			my $opstr= chr($ax_opcode);
			$opstr= "\x48".$opstr if $bits == 64;
			$opstr= "\x66".$opstr if $bits == 16;
			# Do the dance for values which haven't been resolved yet
			my $val= ref $disp? $disp->value : $disp;
			if (!defined $val) {
				$self->_mark_unresolved(
					10, # longest instruction possible, not the greatest guess.
					encode => sub {
						my $v= $disp->value;
						defined $v or croak "Placeholder $disp has not been assigned";
						return $v > 0x7FFFFFFF? $opstr . pack('Q<', $v)
							: ($bits == 16? "\x66":'')
							. $_[0]->_encode_op_reg_mem($bits == 64? 8 : 0, $opcode, 0, undef, $v);
					}
				);
			} else {
				$self->{_buf} .= $opstr . pack('Q<', $val);
			}
			return $self;
		}
	}
	# Else normal encoding for reg,mem
	return $self->_append_op64_reg_mem(8, $opcode, $reg, $mem) if $bits == 64;
	return $self->_append_op32_reg_mem(0, $opcode, $reg, $mem) if $bits == 32;
	return $self->_append_op16_reg_mem(0, $opcode, $reg, $mem) if $bits == 16;
	return $self->_append_op8_reg_mem (0, $opcode, $reg, $mem) if $bits ==  8;
}



sub mov64_reg_imm {
	my ($self, $reg, $immed)= @_;
	$reg= $regnum64{$reg} // croak("$reg is not a 64-bit register");
	$self->_append_possible_unknown('_encode_mov64_imm', [$reg, $immed], 1, 10);
}
sub _encode_mov64_imm {
	my ($self, $reg, $immed)= @_;
	use integer;
	# If the number fits in 32-bits, encode as the classic instruction
	if (!($immed >> 32)) {
		return $reg > 7? # need REX byte if extended register
			pack('CCL<', 0x41, 0xB8 + ($reg&7), $immed)
			: pack('CL<', 0xB8 + $reg, $immed);
	}
	# If the number can sign-extend from 32-bits, encode as 32-bit sign-extend
	elsif (($immed >> 31) == -1) {
		return pack('CCCl<', 0x48 | (($reg & 8) >> 3), 0xC7, 0xC0 + ($reg & 7), $immed);
	}
	# else encode as new 64-bit immediate
	else {
		return pack('CCQ<', 0x48 | (($reg & 8) >> 3), 0xB8 + ($reg & 7), $immed);
	}
}
sub mov32_reg_imm {
	my ($self, $reg, $immed)= @_;
	$reg= $regnum32{$reg} // croak("$reg is not a 32-bit register");
	$self->{_buf} .= "\x41" if $reg > 7;
	$self->{_buf} .= pack('C' , 0xB8 | ($reg & 7));
	$self->_append_possible_unknown(sub { pack('V', $_[1]) }, [$immed], 0, 4);
}
sub mov16_reg_imm {
	my ($self, $reg, $immed)= @_;
	$reg= $regnum16{$reg} // croak("$reg is not a 16-bit register");
	$self->{_buf} .= "\x66";
	$self->{_buf} .= "\x41" if $reg > 7;
	$self->{_buf} .= pack('C', 0xB8 | ($reg & 7));
	$self->_append_possible_unknown(sub { pack('v', $_[1]) }, [$immed], 0, 2);
}
sub mov8_reg_imm {
	my ($self, $reg, $immed)= @_;
	$reg= $regnum8{$reg};
	# Special case for the high-byte registers available without the REX prefix
	if (!defined $reg) {
		$reg= $regnum8_high{$_[1]} // croak("$_[1] is not a 8-bit register");
	} else {
		$self->{_buf} .= pack('C', 0x40|(($reg&8)>>3)) if $reg > 3;
	}
	$self->{_buf} .= pack('C', 0xB0 | ($reg & 7));
	$self->_append_possible_unknown(sub { pack('C', $_[1]&0xFF) }, [$immed], 0, 1);
}


sub mov64_mem_imm { $_[0]->_append_op64_const_to_mem(0xC7, 0, $_[2], $_[1]) }
sub mov32_mem_imm { $_[0]->_append_op32_const_to_mem(0xC7, 0, $_[2], $_[1]) }
sub mov16_mem_imm { $_[0]->_append_op16_const_to_mem(0xC7, 0, $_[2], $_[1]) }
sub mov8_mem_imm  { $_[0]->_append_op8_const_to_mem (0xC6, 0, $_[2], $_[1]) }


sub lea { splice(@_,1,0,'lea'); &_autodetect_signature_dst_src }

sub lea16_reg_reg { $_[0]->_append_op16_reg_reg(   0x8D, $_[1], $_[2]) }
sub lea16_reg_mem { $_[0]->_append_op16_reg_mem(0, 0x8D, $_[1], $_[2]) }
sub lea32_reg_reg { $_[0]->_append_op32_reg_reg(   0x8D, $_[1], $_[2]) }
sub lea32_reg_mem { $_[0]->_append_op32_reg_mem(0, 0x8D, $_[1], $_[2]) }
sub lea64_reg_reg { $_[0]->_append_op64_reg_reg(   0x8D, $_[1], $_[2]) }
sub lea64_reg_mem { $_[0]->_append_op64_reg_mem(8, 0x8D, $_[1], $_[2]) }


sub add { splice(@_,1,0,'add'); &_autodetect_signature_dst_src }

sub add64_reg_reg { $_[0]->_append_op64_reg_reg(0x01, $_[2], $_[1]) }
sub add32_reg_reg { $_[0]->_append_op32_reg_reg(0x01, $_[2], $_[1]) }
sub add16_reg_reg { $_[0]->_append_op16_reg_reg(0x01, $_[2], $_[1]) }
sub add8_reg_reg  { $_[0]->_append_op8_reg_reg (0x00, $_[2], $_[1]) }

sub add64_reg_mem { $_[0]->_append_op64_reg_mem(8, 0x03, $_[1], $_[2]); }
sub add32_reg_mem { $_[0]->_append_op32_reg_mem(0, 0x03, $_[1], $_[2]); }
sub add16_reg_mem { $_[0]->_append_op16_reg_mem(0, 0x03, $_[1], $_[2]); }
sub add8_reg_mem  { $_[0]->_append_op8_reg_mem (0, 0x02, $_[1], $_[2]); }

sub add64_mem_reg { $_[0]->_append_op64_reg_mem(8, 0x01, $_[2], $_[1]); }
sub add32_mem_reg { $_[0]->_append_op32_reg_mem(0, 0x01, $_[2], $_[1]); }
sub add16_mem_reg { $_[0]->_append_op16_reg_mem(0, 0x01, $_[2], $_[1]); }
sub add8_mem_reg  { $_[0]->_append_op8_reg_mem (0, 0x00, $_[2], $_[1]); }

sub add64_reg_imm { shift->_append_mathop64_const(0x05, 0x83, 0x81, 0, @_) }
sub add32_reg_imm { shift->_append_mathop32_const(0x05, 0x83, 0x81, 0, @_) }
sub add16_reg_imm { shift->_append_mathop16_const(0x05, 0x83, 0x81, 0, @_) }
sub add8_reg_imm  { shift->_append_mathop8_const (0x04, 0x80, 0, @_) }

sub add64_mem_imm { $_[0]->_append_mathop64_const_to_mem(0x83, 0x81, 0, $_[2], $_[1]) }
sub add32_mem_imm { $_[0]->_append_mathop32_const_to_mem(0x83, 0x81, 0, $_[2], $_[1]) }
sub add16_mem_imm { $_[0]->_append_mathop16_const_to_mem(0x83, 0x81, 0, $_[2], $_[1]) }
sub add8_mem_imm  { $_[0]->_append_mathop8_const_to_mem (0x80, 0, $_[2], $_[1]) }


sub addcarry { splice(@_,1,0,'addcarry'); &_autodetect_signature_dst_src }
*adc= *addcarry;

sub addcarry64_reg_reg { $_[0]->_append_op64_reg_reg(0x11, $_[2], $_[1]) }
sub addcarry32_reg_reg { $_[0]->_append_op32_reg_reg(0x11, $_[2], $_[1]) }
sub addcarry16_reg_reg { $_[0]->_append_op16_reg_reg(0x11, $_[2], $_[1]) }
sub addcarry8_reg_reg  { $_[0]->_append_op8_reg_reg (0x10, $_[2], $_[1]) }

sub addcarry64_reg_mem { $_[0]->_append_op64_reg_mem(8, 0x13, $_[1], $_[2]); }
sub addcarry32_reg_mem { $_[0]->_append_op32_reg_mem(0, 0x13, $_[1], $_[2]); }
sub addcarry16_reg_mem { $_[0]->_append_op16_reg_mem(0, 0x13, $_[1], $_[2]); }
sub addcarry8_reg_mem  { $_[0]->_append_op8_reg_mem (0, 0x12, $_[1], $_[2]); }

sub addcarry64_mem_reg { $_[0]->_append_op64_reg_mem(8, 0x11, $_[2], $_[1]); }
sub addcarry32_mem_reg { $_[0]->_append_op32_reg_mem(0, 0x11, $_[2], $_[1]); }
sub addcarry16_mem_reg { $_[0]->_append_op16_reg_mem(0, 0x11, $_[2], $_[1]); }
sub addcarry8_mem_reg  { $_[0]->_append_op8_reg_mem (0, 0x10, $_[2], $_[1]); }

sub addcarry64_reg_imm { shift->_append_mathop64_const(0x15, 0x83, 0x81, 2, @_) }
sub addcarry32_reg_imm { shift->_append_mathop32_const(0x15, 0x83, 0x81, 2, @_) }
sub addcarry16_reg_imm { shift->_append_mathop16_const(0x15, 0x83, 0x81, 2, @_) }
sub addcarry8_reg_imm  { shift->_append_mathop8_const (0x14, 0x80, 2, @_) }

sub addcarry64_mem_imm { $_[0]->_append_mathop64_const_to_mem(0x83, 0x81, 2, $_[2], $_[1]) }
sub addcarry32_mem_imm { $_[0]->_append_mathop32_const_to_mem(0x83, 0x81, 2, $_[2], $_[1]) }
sub addcarry16_mem_imm { $_[0]->_append_mathop16_const_to_mem(0x83, 0x81, 2, $_[2], $_[1]) }
sub addcarry8_mem_imm  { $_[0]->_append_mathop8_const_to_mem (0x80, 2, $_[2], $_[1]) }


sub sub { splice(@_,1,0,'sub'); &_autodetect_signature_dst_src }

sub sub64_reg_reg { $_[0]->_append_op64_reg_reg(0x29, $_[2], $_[1]) }
sub sub32_reg_reg { $_[0]->_append_op32_reg_reg(0x29, $_[2], $_[1]) }
sub sub16_reg_reg { $_[0]->_append_op16_reg_reg(0x29, $_[2], $_[1]) }
sub sub8_reg_reg  { $_[0]->_append_op8_reg_reg (0x28, $_[2], $_[1]) }

sub sub64_reg_mem { $_[0]->_append_op64_reg_mem(8, 0x2B, $_[1], $_[2]); }
sub sub32_reg_mem { $_[0]->_append_op32_reg_mem(0, 0x2B, $_[1], $_[2]); }
sub sub16_reg_mem { $_[0]->_append_op16_reg_mem(0, 0x2B, $_[1], $_[2]); }
sub sub8_reg_mem  { $_[0]->_append_op8_reg_mem (0, 0x2A, $_[1], $_[2]); }

sub sub64_mem_reg { $_[0]->_append_op64_reg_mem(8, 0x29, $_[2], $_[1]); }
sub sub32_mem_reg { $_[0]->_append_op32_reg_mem(0, 0x29, $_[2], $_[1]); }
sub sub16_mem_reg { $_[0]->_append_op16_reg_mem(0, 0x29, $_[2], $_[1]); }
sub sub8_mem_reg  { $_[0]->_append_op8_reg_mem (0, 0x28, $_[2], $_[1]); }

sub sub64_reg_imm { shift->_append_mathop64_const(0x2D, 0x83, 0x81, 5, @_) }
sub sub32_reg_imm { shift->_append_mathop32_const(0x2D, 0x83, 0x81, 5, @_) }
sub sub16_reg_imm { shift->_append_mathop16_const(0x2D, 0x83, 0x81, 5, @_) }
sub sub8_reg_imm  { shift->_append_mathop8_const (0x2C, 0x80, 5, @_) }

sub sub64_mem_imm { $_[0]->_append_mathop64_const_to_mem(0x83, 0x81, 5, $_[2], $_[1]) }
sub sub32_mem_imm { $_[0]->_append_mathop32_const_to_mem(0x83, 0x81, 5, $_[2], $_[1]) }
sub sub16_mem_imm { $_[0]->_append_mathop16_const_to_mem(0x83, 0x81, 5, $_[2], $_[1]) }
sub sub8_mem_imm  { $_[0]->_append_mathop8_const_to_mem (0x80, 5, $_[2], $_[1]) }


sub and { splice(@_,1,0,'and'); &_autodetect_signature_dst_src }

sub and64_reg_reg { $_[0]->_append_op64_reg_reg(0x21, $_[2], $_[1]) }
sub and32_reg_reg { $_[0]->_append_op32_reg_reg(0x21, $_[2], $_[1]) }
sub and16_reg_reg { $_[0]->_append_op16_reg_reg(0x21, $_[2], $_[1]) }
sub and8_reg_reg  { $_[0]->_append_op8_reg_reg (0x20, $_[2], $_[1]) }

sub and64_reg_mem { $_[0]->_append_op64_reg_mem(8, 0x23, $_[1], $_[2]); }
sub and32_reg_mem { $_[0]->_append_op32_reg_mem(0, 0x23, $_[1], $_[2]); }
sub and16_reg_mem { $_[0]->_append_op16_reg_mem(0, 0x23, $_[1], $_[2]); }
sub and8_reg_mem  { $_[0]->_append_op8_reg_mem (0, 0x22, $_[1], $_[2]); }

sub and64_mem_reg { $_[0]->_append_op64_reg_mem(8, 0x21, $_[2], $_[1]); }
sub and32_mem_reg { $_[0]->_append_op32_reg_mem(0, 0x21, $_[2], $_[1]); }
sub and16_mem_reg { $_[0]->_append_op16_reg_mem(0, 0x21, $_[2], $_[1]); }
sub and8_mem_reg  { $_[0]->_append_op8_reg_mem (0, 0x20, $_[2], $_[1]); }

sub and64_reg_imm { shift->_append_mathop64_const(0x25, 0x83, 0x81, 4, @_) }
sub and32_reg_imm { shift->_append_mathop32_const(0x25, 0x83, 0x81, 4, @_) }
sub and16_reg_imm { shift->_append_mathop16_const(0x25, 0x83, 0x81, 4, @_) }
sub and8_reg_imm  { shift->_append_mathop8_const (0x24, 0x80, 4, @_) }

sub and64_mem_imm { $_[0]->_append_mathop64_const_to_mem(0x83, 0x81, 4, $_[2], $_[1]) }
sub and32_mem_imm { $_[0]->_append_mathop32_const_to_mem(0x83, 0x81, 4, $_[2], $_[1]) }
sub and16_mem_imm { $_[0]->_append_mathop16_const_to_mem(0x83, 0x81, 4, $_[2], $_[1]) }
sub and8_mem_imm  { $_[0]->_append_mathop8_const_to_mem (0x80, 4, $_[2], $_[1]) }


sub or { splice(@_,1,0,'or'); &_autodetect_signature_dst_src }

sub or64_reg_reg { $_[0]->_append_op64_reg_reg(0x09, $_[2], $_[1]) }
sub or32_reg_reg { $_[0]->_append_op32_reg_reg(0x09, $_[2], $_[1]) }
sub or16_reg_reg { $_[0]->_append_op16_reg_reg(0x09, $_[2], $_[1]) }
sub or8_reg_reg  { $_[0]->_append_op8_reg_reg (0x08, $_[2], $_[1]) }

sub or64_reg_mem { $_[0]->_append_op64_reg_mem(8, 0x0B, $_[1], $_[2]); }
sub or32_reg_mem { $_[0]->_append_op32_reg_mem(0, 0x0B, $_[1], $_[2]); }
sub or16_reg_mem { $_[0]->_append_op16_reg_mem(0, 0x0B, $_[1], $_[2]); }
sub or8_reg_mem  { $_[0]->_append_op8_reg_mem (0, 0x0A, $_[1], $_[2]); }

sub or64_mem_reg { $_[0]->_append_op64_reg_mem(8, 0x09, $_[2], $_[1]); }
sub or32_mem_reg { $_[0]->_append_op32_reg_mem(0, 0x09, $_[2], $_[1]); }
sub or16_mem_reg { $_[0]->_append_op16_reg_mem(0, 0x09, $_[2], $_[1]); }
sub or8_mem_reg  { $_[0]->_append_op8_reg_mem (0, 0x08, $_[2], $_[1]); }

sub or64_reg_imm { shift->_append_mathop64_const(0x0D, 0x83, 0x81, 1, @_) }
sub or32_reg_imm { shift->_append_mathop32_const(0x0D, 0x83, 0x81, 1, @_) }
sub or16_reg_imm { shift->_append_mathop16_const(0x0D, 0x83, 0x81, 1, @_) }
sub or8_reg_imm  { shift->_append_mathop8_const (0x0C, 0x80, 1, @_) }

sub or64_mem_imm { $_[0]->_append_mathop64_const_to_mem(0x83, 0x81, 1, $_[2], $_[1]) }
sub or32_mem_imm { $_[0]->_append_mathop32_const_to_mem(0x83, 0x81, 1, $_[2], $_[1]) }
sub or16_mem_imm { $_[0]->_append_mathop16_const_to_mem(0x83, 0x81, 1, $_[2], $_[1]) }
sub or8_mem_imm  { $_[0]->_append_mathop8_const_to_mem (0x80, 1, $_[2], $_[1]) }


sub xor { splice(@_,1,0,'xor'); &_autodetect_signature_dst_src }

sub xor64_reg_reg { $_[0]->_append_op64_reg_reg(0x31, $_[2], $_[1]) }
sub xor32_reg_reg { $_[0]->_append_op32_reg_reg(0x31, $_[2], $_[1]) }
sub xor16_reg_reg { $_[0]->_append_op16_reg_reg(0x31, $_[2], $_[1]) }
sub xor8_reg_reg  { $_[0]->_append_op8_reg_reg (0x30, $_[2], $_[1]) }

sub xor64_reg_mem { $_[0]->_append_op64_reg_mem(8, 0x33, $_[1], $_[2]); }
sub xor32_reg_mem { $_[0]->_append_op32_reg_mem(0, 0x33, $_[1], $_[2]); }
sub xor16_reg_mem { $_[0]->_append_op16_reg_mem(0, 0x33, $_[1], $_[2]); }
sub xor8_reg_mem  { $_[0]->_append_op8_reg_mem (0, 0x32, $_[1], $_[2]); }

sub xor64_mem_reg { $_[0]->_append_op64_reg_mem(8, 0x31, $_[2], $_[1]); }
sub xor32_mem_reg { $_[0]->_append_op32_reg_mem(0, 0x31, $_[2], $_[1]); }
sub xor16_mem_reg { $_[0]->_append_op16_reg_mem(0, 0x31, $_[2], $_[1]); }
sub xor8_mem_reg  { $_[0]->_append_op8_reg_mem (0, 0x30, $_[2], $_[1]); }

sub xor64_reg_imm { shift->_append_mathop64_const(0x35, 0x83, 0x81, 6, @_) }
sub xor32_reg_imm { shift->_append_mathop32_const(0x35, 0x83, 0x81, 6, @_) }
sub xor16_reg_imm { shift->_append_mathop16_const(0x35, 0x83, 0x81, 6, @_) }
sub xor8_reg_imm  { shift->_append_mathop8_const (0x34, 0x80, 6, @_) }

sub xor64_mem_imm { $_[0]->_append_mathop64_const_to_mem(0x83, 0x81, 6, $_[2], $_[1]) }
sub xor32_mem_imm { $_[0]->_append_mathop32_const_to_mem(0x83, 0x81, 6, $_[2], $_[1]) }
sub xor16_mem_imm { $_[0]->_append_mathop16_const_to_mem(0x83, 0x81, 6, $_[2], $_[1]) }
sub xor8_mem_imm  { $_[0]->_append_mathop8_const_to_mem (0x80, 6, $_[2], $_[1]) }


sub shl { splice(@_,1,0,'shl'); &_autodetect_signature_dst_src }

sub shl64_reg_imm { $_[0]->_append_shiftop_reg_imm(64, 0xD1, 0xC1, 4, $_[1], $_[2]) }
sub shl32_reg_imm { $_[0]->_append_shiftop_reg_imm(32, 0xD1, 0xC1, 4, $_[1], $_[2]) }
sub shl16_reg_imm { $_[0]->_append_shiftop_reg_imm(16, 0xD1, 0xC1, 4, $_[1], $_[2]) }
sub shl8_reg_imm  { $_[0]->_append_shiftop_reg_imm( 8, 0xD0, 0xC0, 4, $_[1], $_[2]) }

sub shl64_reg_cl  { $_[0]->_append_op64_reg_reg(0xD3, 4, $_[1]) }
sub shl32_reg_cl  { $_[0]->_append_op32_reg_reg(0xD3, 4, $_[1]) }
sub shl16_reg_cl  { $_[0]->_append_op16_reg_reg(0xD3, 4, $_[1]) }
sub shl8_reg_cl   { $_[0]->_append_op8_opreg_reg(0xD2, 4, $_[1]) }

sub shl64_mem_imm { $_[0]->_append_shiftop_mem_imm(64, 0xD1, 0xC1, 4, $_[1], $_[2]) }
sub shl32_mem_imm { $_[0]->_append_shiftop_mem_imm(32, 0xD1, 0xC1, 4, $_[1], $_[2]) }
sub shl16_mem_imm { $_[0]->_append_shiftop_mem_imm(16, 0xD1, 0xC1, 4, $_[1], $_[2]) }
sub shl8_mem_imm  { $_[0]->_append_shiftop_mem_imm( 8, 0xD0, 0xC0, 4, $_[1], $_[2]) }

sub shl64_mem_cl  { $_[0]->_append_op64_reg_mem(8, 0xD3, 4, $_[1]) }
sub shl32_mem_cl  { $_[0]->_append_op32_reg_mem(0, 0xD3, 4, $_[1]) }
sub shl16_mem_cl  { $_[0]->_append_op16_reg_mem(0, 0xD3, 4, $_[1]) }
sub shl8_mem_cl   { $_[0]->_append_op8_opreg_mem(0, 0xD2, 4, $_[1]) }


sub shr { splice(@_,1,0,'shr'); &_autodetect_signature_dst_src }

sub shr64_reg_imm { $_[0]->_append_shiftop_reg_imm(64, 0xD1, 0xC1, 5, $_[1], $_[2]) }
sub shr32_reg_imm { $_[0]->_append_shiftop_reg_imm(32, 0xD1, 0xC1, 5, $_[1], $_[2]) }
sub shr16_reg_imm { $_[0]->_append_shiftop_reg_imm(16, 0xD1, 0xC1, 5, $_[1], $_[2]) }
sub shr8_reg_imm  { $_[0]->_append_shiftop_reg_imm( 8, 0xD0, 0xC0, 5, $_[1], $_[2]) }

sub shr64_reg_cl  { $_[0]->_append_op64_reg_reg(0xD3, 5, $_[1]) }
sub shr32_reg_cl  { $_[0]->_append_op32_reg_reg(0xD3, 5, $_[1]) }
sub shr16_reg_cl  { $_[0]->_append_op16_reg_reg(0xD3, 5, $_[1]) }
sub shr8_reg_cl   { $_[0]->_append_op8_opreg_reg(0xD2, 5, $_[1]) }

sub shr64_mem_imm { $_[0]->_append_shiftop_mem_imm(64, 0xD1, 0xC1, 5, $_[1], $_[2]) }
sub shr32_mem_imm { $_[0]->_append_shiftop_mem_imm(32, 0xD1, 0xC1, 5, $_[1], $_[2]) }
sub shr16_mem_imm { $_[0]->_append_shiftop_mem_imm(16, 0xD1, 0xC1, 5, $_[1], $_[2]) }
sub shr8_mem_imm  { $_[0]->_append_shiftop_mem_imm( 8, 0xD0, 0xC0, 5, $_[1], $_[2]) }

sub shr64_mem_cl  { $_[0]->_append_op64_reg_mem(8, 0xD3, 5, $_[1]) }
sub shr32_mem_cl  { $_[0]->_append_op32_reg_mem(0, 0xD3, 5, $_[1]) }
sub shr16_mem_cl  { $_[0]->_append_op16_reg_mem(0, 0xD3, 5, $_[1]) }
sub shr8_mem_cl   { $_[0]->_append_op8_opreg_mem(0, 0xD2, 5, $_[1]) }


sub sar { splice(@_,1,0,'sar'); &_autodetect_signature_dst_src }

sub sar64_reg_imm { $_[0]->_append_shiftop_reg_imm(64, 0xD1, 0xC1, 7, $_[1], $_[2]) }
sub sar32_reg_imm { $_[0]->_append_shiftop_reg_imm(32, 0xD1, 0xC1, 7, $_[1], $_[2]) }
sub sar16_reg_imm { $_[0]->_append_shiftop_reg_imm(16, 0xD1, 0xC1, 7, $_[1], $_[2]) }
sub sar8_reg_imm  { $_[0]->_append_shiftop_reg_imm( 8, 0xD0, 0xC0, 7, $_[1], $_[2]) }

sub sar64_reg_cl  { $_[0]->_append_op64_reg_reg(0xD3, 7, $_[1]) }
sub sar32_reg_cl  { $_[0]->_append_op32_reg_reg(0xD3, 7, $_[1]) }
sub sar16_reg_cl  { $_[0]->_append_op16_reg_reg(0xD3, 7, $_[1]) }
sub sar8_reg_cl   { $_[0]->_append_op8_opreg_reg(0xD2, 7, $_[1]) }

sub sar64_mem_imm { $_[0]->_append_shiftop_mem_imm(64, 0xD1, 0xC1, 7, $_[1], $_[2]) }
sub sar32_mem_imm { $_[0]->_append_shiftop_mem_imm(32, 0xD1, 0xC1, 7, $_[1], $_[2]) }
sub sar16_mem_imm { $_[0]->_append_shiftop_mem_imm(16, 0xD1, 0xC1, 7, $_[1], $_[2]) }
sub sar8_mem_imm  { $_[0]->_append_shiftop_mem_imm( 8, 0xD0, 0xC0, 7, $_[1], $_[2]) }

sub sar64_mem_cl  { $_[0]->_append_op64_reg_mem(8, 0xD3, 7, $_[1]) }
sub sar32_mem_cl  { $_[0]->_append_op32_reg_mem(0, 0xD3, 7, $_[1]) }
sub sar16_mem_cl  { $_[0]->_append_op16_reg_mem(0, 0xD3, 7, $_[1]) }
sub sar8_mem_cl   { $_[0]->_append_op8_opreg_mem(0, 0xD2, 7, $_[1]) }


sub cmp { splice(@_,1,0,'cmp'); &_autodetect_signature_dst_src }

sub cmp64_reg_reg { $_[0]->_append_op64_reg_reg(0x39, $_[2], $_[1]) }
sub cmp32_reg_reg { $_[0]->_append_op32_reg_reg(0x39, $_[2], $_[1]) }
sub cmp16_reg_reg { $_[0]->_append_op16_reg_reg(0x39, $_[2], $_[1]) }
sub cmp8_reg_reg  { $_[0]->_append_op8_reg_reg (0x38, $_[2], $_[1]) }

sub cmp64_reg_mem { $_[0]->_append_op64_reg_mem(8, 0x3B, $_[1], $_[2]); }
sub cmp32_reg_mem { $_[0]->_append_op32_reg_mem(0, 0x3B, $_[1], $_[2]); }
sub cmp16_reg_mem { $_[0]->_append_op16_reg_mem(0, 0x3B, $_[1], $_[2]); }
sub cmp8_reg_mem  { $_[0]->_append_op8_reg_mem (0, 0x3A, $_[1], $_[2]); }

sub cmp64_mem_reg { $_[0]->_append_op64_reg_mem(8, 0x39, $_[2], $_[1]); }
sub cmp32_mem_reg { $_[0]->_append_op32_reg_mem(0, 0x39, $_[2], $_[1]); }
sub cmp16_mem_reg { $_[0]->_append_op16_reg_mem(0, 0x39, $_[2], $_[1]); }
sub cmp8_mem_reg  { $_[0]->_append_op8_reg_mem (0, 0x38, $_[2], $_[1]); }

sub cmp64_reg_imm { shift->_append_mathop64_const(0x3D, 0x83, 0x81, 7, @_) }
sub cmp32_reg_imm { shift->_append_mathop32_const(0x3D, 0x83, 0x81, 7, @_) }
sub cmp16_reg_imm { shift->_append_mathop16_const(0x3D, 0x83, 0x81, 7, @_) }
sub cmp8_reg_imm  { shift->_append_mathop8_const (0x3C, 0x80, 7, @_) }

sub cmp64_mem_imm { $_[0]->_append_mathop64_const_to_mem(0x83, 0x81, 7, $_[2], $_[1]) }
sub cmp32_mem_imm { $_[0]->_append_mathop32_const_to_mem(0x83, 0x81, 7, $_[2], $_[1]) }
sub cmp16_mem_imm { $_[0]->_append_mathop16_const_to_mem(0x83, 0x81, 7, $_[2], $_[1]) }
sub cmp8_mem_imm  { $_[0]->_append_mathop8_const_to_mem (0x80, 7, $_[2], $_[1]) }


sub test { splice(@_,1,0,'test'); &_autodetect_signature_dst_src }

sub test64_reg_reg { $_[0]->_append_op64_reg_reg(0x85, $_[2], $_[1]) }
sub test32_reg_reg { $_[0]->_append_op32_reg_reg(0x85, $_[2], $_[1]) }
sub test16_reg_reg { $_[0]->_append_op16_reg_reg(0x85, $_[2], $_[1]) }
sub test8_reg_reg  { $_[0]->_append_op8_reg_reg (0x84, $_[2], $_[1]) }

sub test64_reg_mem { $_[0]->_append_op64_reg_mem(8, 0x85, $_[1], $_[2]); }
sub test32_reg_mem { $_[0]->_append_op32_reg_mem(0, 0x85, $_[1], $_[2]); }
sub test16_reg_mem { $_[0]->_append_op16_reg_mem(0, 0x85, $_[1], $_[2]); }
sub test8_reg_mem  { $_[0]->_append_op8_reg_mem (0, 0x84, $_[1], $_[2]); }

sub test64_reg_imm { $_[0]->_append_mathop64_const(0xA9, undef, 0xF7, 0, $_[1], $_[2]) }
sub test32_reg_imm { $_[0]->_append_mathop32_const(0xA9, undef, 0xF7, 0, $_[1], $_[2]) }
sub test16_reg_imm { $_[0]->_append_mathop16_const(0xA9, undef, 0xF7, 0, $_[1], $_[2]) }
sub test8_reg_imm  { $_[0]->_append_mathop8_const (0xA8, 0xF6, 0, $_[1], $_[2]) }

sub test64_mem_imm { $_[0]->_append_mathop64_const_to_mem(undef, 0xF7, 0, $_[2], $_[1]) }
sub test32_mem_imm { $_[0]->_append_mathop32_const_to_mem(undef, 0xF7, 0, $_[2], $_[1]) }
sub test16_mem_imm { $_[0]->_append_mathop16_const_to_mem(undef, 0xF7, 0, $_[2], $_[1]) }
sub test8_mem_imm  { $_[0]->_append_mathop8_const_to_mem (0xF6, 0, $_[2], $_[1]) }


sub dec { splice(@_,1,0,'dec'); &_autodetect_signature_1op; }

sub dec64_reg { $_[0]->_append_op64_reg_reg(0xFF, 1, $_[1]) }
sub dec32_reg { $_[0]->_append_op32_reg_reg(0xFF, 1, $_[1]) }
sub dec16_reg { $_[0]->_append_op16_reg_reg(0xFF, 1, $_[1]) }
sub dec8_reg  { $_[0]->_append_op8_reg_reg (0xFE, 1, $_[1]) }

sub dec64_mem { $_[0]->_append_op64_reg_mem(8, 0xFF, 1, $_[1]) }
sub dec32_mem { $_[0]->_append_op32_reg_mem(0, 0xFF, 1, $_[1]) }
sub dec16_mem { $_[0]->_append_op16_reg_mem(0, 0xFF, 1, $_[1]) }
sub dec8_mem  { $_[0]->_append_op8_reg_mem (0, 0xFE, 1, $_[1]) }


sub inc { splice(@_,1,0,'inc'); &_autodetect_signature_1op; }

sub inc64_reg { $_[0]->_append_op64_reg_reg(0xFF, 0, $_[1]) }
sub inc32_reg { $_[0]->_append_op32_reg_reg(0xFF, 0, $_[1]) }
sub inc16_reg { $_[0]->_append_op16_reg_reg(0xFF, 0, $_[1]) }
sub inc8_reg  { $_[0]->_append_op8_reg_reg (0xFE, 0, $_[1]) }

sub inc64_mem { $_[0]->_append_op64_reg_mem(8, 0xFF, 0, $_[1]) }
sub inc32_mem { $_[0]->_append_op32_reg_mem(0, 0xFF, 0, $_[1]) }
sub inc16_mem { $_[0]->_append_op16_reg_mem(0, 0xFF, 0, $_[1]) }
sub inc8_mem  { $_[0]->_append_op8_reg_mem (0, 0xFE, 0, $_[1]) }


sub not { splice(@_,1,0,'not'); &_autodetect_signature_1op; }

sub not64_reg { $_[0]->_append_op64_reg_reg(0xF7, 2, $_[1]) }
sub not32_reg { $_[0]->_append_op32_reg_reg(0xF7, 2, $_[1]) }
sub not16_reg { $_[0]->_append_op16_reg_reg(0xF7, 2, $_[1]) }
sub not8_reg  { $_[0]->_append_op8_reg_reg (0xF6, 2, $_[1]) }

sub not64_mem { $_[0]->_append_op64_reg_mem(8, 0xF7, 2, $_[1]) }
sub not32_mem { $_[0]->_append_op32_reg_mem(0, 0xF7, 2, $_[1]) }
sub not16_mem { $_[0]->_append_op16_reg_mem(0, 0xF7, 2, $_[1]) }
sub not8_mem  { $_[0]->_append_op8_reg_mem (0, 0xF6, 2, $_[1]) }


sub neg { splice(@_,1,0,'neg'); &_autodetect_signature_1op; }

sub neg64_reg { $_[0]->_append_op64_reg_reg(0xF7, 3, $_[1]) }
sub neg32_reg { $_[0]->_append_op32_reg_reg(0xF7, 3, $_[1]) }
sub neg16_reg { $_[0]->_append_op16_reg_reg(0xF7, 3, $_[1]) }
sub neg8_reg  { $_[0]->_append_op8_reg_reg (0xF6, 3, $_[1]) }

sub neg64_mem { $_[0]->_append_op64_reg_mem(8, 0xF7, 3, $_[1]) }
sub neg32_mem { $_[0]->_append_op32_reg_mem(0, 0xF7, 3, $_[1]) }
sub neg16_mem { $_[0]->_append_op16_reg_mem(0, 0xF7, 3, $_[1]) }
sub neg8_mem  { $_[0]->_append_op8_reg_mem (0, 0xF6, 3, $_[1]) }


sub div  { splice(@_,1,0,'div' ); &_autodetect_signature_1op; }
sub idiv { splice(@_,1,0,'idiv'); &_autodetect_signature_1op; }

sub div64_reg { $_[0]->_append_op64_reg_reg (0xF7, 6, $_[1]) }
sub div32_reg { $_[0]->_append_op32_reg_reg (0xF7, 6, $_[1]) }
sub div16_reg { $_[0]->_append_op16_reg_reg (0xF7, 6, $_[1]) }
sub div8_reg  { $_[0]->_append_op8_opreg_reg(0xF6, 6, $_[1]) }

sub div64_mem { $_[0]->_append_op64_reg_mem (8, 0xF7, 6, $_[1]) }
sub div32_mem { $_[0]->_append_op32_reg_mem (0, 0xF7, 6, $_[1]) }
sub div16_mem { $_[0]->_append_op16_reg_mem (0, 0xF7, 6, $_[1]) }
sub div8_mem  { $_[0]->_append_op8_opreg_mem(0, 0xF6, 6, $_[1]) }

sub idiv64_reg { $_[0]->_append_op64_reg_reg (0xF7, 7, $_[1]) }
sub idiv32_reg { $_[0]->_append_op32_reg_reg (0xF7, 7, $_[1]) }
sub idiv16_reg { $_[0]->_append_op16_reg_reg (0xF7, 7, $_[1]) }
sub idiv8_reg  { $_[0]->_append_op8_opreg_reg(0xF6, 7, $_[1]) }

sub idiv64_mem { $_[0]->_append_op64_reg_mem (8, 0xF7, 7, $_[1]) }
sub idiv32_mem { $_[0]->_append_op32_reg_mem (0, 0xF7, 7, $_[1]) }
sub idiv16_mem { $_[0]->_append_op16_reg_mem (0, 0xF7, 7, $_[1]) }
sub idiv8_mem  { $_[0]->_append_op8_opreg_mem(0, 0xF6, 7, $_[1]) }


#=item mul64_reg
#
#=item mul32_reg
#
#=item mul16_reg
#
#=item mul64_mem
#
#=item mul32_mem
#
#=item mul16_mem
#
#=item mul64_reg_imm
#
#=item mul32_reg_imm
#
#=item mul16_reg_imm
#
#=item mul64_mem_imm
#
#=item mul32_mem_imm
#
#=item mul16_mem_imm

sub mul64_dxax_reg { shift->_append_op64_reg_reg(8, 0xF7, 5, @_) }
sub mul32_dxax_reg { shift->_append_op32_reg_reg(0, 0xF7, 5, @_) }
sub mul16_dxax_reg { shift->_append_op16_reg_reg(0, 0xF7, 5, @_) }
sub mul8_ax_reg    { shift->_append_op8_reg_reg (0, 0xF6, 5, @_) }

#sub mul64s_reg { shift->_append_op64_reg_reg(8,


sub sign_extend_al_ax { $_[0]{_buf} .= "\x66\x98"; $_[0] }
*cbw= *sign_extend_al_ax;

sub sign_extend_ax_eax { $_[0]{_buf} .= "\x98"; $_[0] }
*cwde= *sign_extend_ax_eax;

sub sign_extend_eax_rax { $_[0]{_buf} .= "\x48\x98"; $_[0] }
*cdqe= *sign_extend_eax_rax;

sub sign_extend_ax_dx { $_[0]{_buf} .= "\x66\x99"; $_[0] }
*cwd= *sign_extend_ax_dx;

sub sign_extend_eax_edx { $_[0]{_buf} .= "\x99"; $_[0] }
*cdq= *sign_extend_eax_edx;

sub sign_extend_rax_rdx { $_[0]{_buf} .= "\x48\x99"; $_[0] }
*cqo= *sign_extend_rax_rdx;


my @_carry_flag_op= ( "\xF5", "\xF8", "\xF9" );
sub flag_carry { $_[0]{_buf} .= $_carry_flag_op[$_[1] + 1]; $_[0] }
sub clc { $_[0]{_buf} .= "\xF8"; $_[0] }
sub cmc { $_[0]{_buf} .= "\xF5"; $_[0] }
sub stc { $_[0]{_buf} .= "\xF9"; $_[0] }


# wait til late in compilation to avoid name clash hassle
END { eval q|sub push { splice(@_,1,0,'push' ); &_autodetect_signature_1op; }| };

sub push_reg {
	my ($self, $reg)= @_;
	$reg= ($regnum64{$reg} // croak("$reg is not a 64-bit register"));
	$self->{_buf} .= $reg > 7? pack('CC', 0x41, 0x50+($reg&7)) : pack('C', 0x50+($reg&7));
	$self;
}

sub push_imm {
	my ($self, $imm)= @_;
	use integer;
	my $val= ref $imm? 0x7FFFFFFF : $imm;
	$self->{_buf} .= (($val >> 7) == ($val >> 8))? pack('Cc', 0x6A, $val) : pack('CV', 0x68, $val);
	$self->_mark_unresolved(-4, encode => '_repack', bits => 32, value => $imm)
		if ref $imm;
	$self;
}

sub push_mem { shift->_append_op64_reg_mem(0, 0xFF, 6, shift) }


# wait til late in compilation to avoid name clash hassle
END { eval q|sub pop { splice(@_,1,0,'pop' ); &_autodetect_signature_1op; }| };

sub pop_reg {
	my ($self, $reg)= @_;
	$reg= ($regnum64{$reg} // croak("$reg is not a 64-bit register"));
	$self->{_buf} .= $reg > 7? pack('CC', 0x41, 0x58+($reg&7)) : pack('C', 0x58+($reg&7));
	$self;
}

sub pop_mem { shift->_append_op64_reg_mem(0, 0x8F, 0, shift) }


sub enter {
	my ($self, $varspace, $nesting)= @_;
	$nesting //= 0;
	if (!ref $varspace && !ref $nesting) {
		$self->{_buf} .= pack('CvC', 0xC8, $varspace, $nesting);
	}
	else {
		$self->{_buf} .= pack('Cv', 0xC8, ref $varspace? 0 : $varspace);
		$self->_mark_unresolved(-2, encode => '_repack', bits => 16, value => $varspace)
			if ref $varspace;
		$self->{_buf} .= pack('C', ref $nesting? 0 : $nesting);
		$self->_mark_unresolved(-1, encode => '_repack', bits => 8, value => $nesting)
			if ref $nesting;
	}
	$self
}


sub leave { $_[0]{_buf} .= "\xC9"; $_[0] }


sub syscall {
	$_[0]{_buf} .= "\x0F\x05";
	$_[0];
}


sub rep { $_[0]{_buf} .= "\xF3"; $_[0] }
*repe= *repz= *rep;

sub repnz { $_[0]{_buf} .= "\xF2"; $_[0] }
*repne= *repnz;


my @_direction_flag_op= ( "\xFC", "\xFD" );
sub flag_direction { $_[0]{_buf} .= $_direction_flag_op[0+!!$_[1]]; $_[0] }
sub cld { $_[0]{_buf} .= "\xFC"; $_[0] }
sub std { $_[0]{_buf} .= "\xFD"; $_[0] }


sub movs64 { $_[0]{_buf} .= "\x48\xA5"; $_[0] }
*movsq= *movs64;

sub movs32 { $_[0]{_buf} .= "\xA5"; $_[0] }
*movsd= *movs32;

sub movs16 { $_[0]{_buf} .= "\x66\xA5"; $_[0] }
*movsw= *movs16;

sub movs8  { $_[0]{_buf} .= "\xA4"; $_[0] }
*movsb= *movs8;


sub cmps64 { $_[0]{_buf}.= "\x48\xA7"; $_[0] }
*cmpsq= *cmps64;

sub cmps32 { $_[0]{_buf}.= "\xA7"; $_[0] }
*cmpsd= *cmps32;

sub cmps16 { $_[0]{_buf}.= "\x66\xA7"; $_[0] }
*cmpsw= *cmps16;

sub cmps8  { $_[0]{_buf}.= "\xA6"; $_[0] }
*cmpsb= *cmps8;


sub scas64 { $_[0]{_buf} .= "\x48\xAF"; $_[0] }
*scasq= *scas64;

sub scas32 { $_[0]{_buf} .= "\xAF"; $_[0] }
*scasd= *scas32;

sub scas16 { $_[0]{_buf} .= "\x66\xAF"; $_[0] }
*scasw= *scas16;

sub scas8 { $_[0]{_buf} .= "\xAE"; $_[0] }
*scasb= *scas8;


sub mfence {
	$_[0]{_buf} .= "\x0F\xAE\xF0";
	$_[0];
}
sub lfence {
	$_[0]{_buf} .= "\x0F\xAE\xE8";
	$_[0];
}
sub sfence {
	$_[0]{_buf} .= "\x0F\xAE\xF8";
	$_[0];
}

#sub cache_flush {
#	...;
#}
#*clflush= *cache_flush;


#=head2 _encode_op_reg_reg
#
#Encode standard instruction with REX prefix which refers only to registers.
#This skips all the memory addressing logic since it is only operating on registers,
#and always produces known-length encodings.
#
#=cut

sub _encode_op_reg_reg {
	my ($self, $rex, $opcode, $reg1, $reg2, $immed_pack, $immed)= @_;
	use integer;
	$rex |= (($reg1 & 8) >> 1) | (($reg2 & 8) >> 3);
	return $rex?
		(defined $immed?
			pack('CCC'.$immed_pack, 0x40|$rex, $opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7), $immed)
			: pack('CCC', 0x40|$rex, $opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7))
		)
		: (defined $immed?
			pack('CC'.$immed_pack, $opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7), $immed)
			: pack('CC', $opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7))
		);
}

sub _append_op64_reg_reg {
	my ($self, $opcode, $reg1, $reg2)= @_;
	$reg1= ($regnum64{$reg1} // croak("$reg1 is not a 64-bit register"));
	$reg2= ($regnum64{$reg2} // croak("$reg2 is not a 64-bit register"));
	use integer;
	$self->{_buf} .= pack('CCC',
		0x48 | (($reg1 & 8) >> 1) | (($reg2 & 8) >> 3),
		$opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7));
	$self;
}
sub _append_op32_reg_reg {
	my ($self, $opcode, $reg1, $reg2)= @_;
	$reg1= ($regnum32{$reg1} // croak("$reg1 is not a 32-bit register"));
	$reg2= ($regnum32{$reg2} // croak("$reg2 is not a 32-bit register"));
	use integer;
	my $rex= (($reg1 & 8) >> 1) | (($reg2 & 8) >> 3);
	$self->{_buf} .= $rex?
		pack('CCC', 0x40|$rex, $opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7))
		: pack('CC', $opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7));
	$self;
}
sub _append_op16_reg_reg {
	my ($self, $opcode, $reg1, $reg2)= @_;
	$reg1= ($regnum16{$reg1} // croak("$reg1 is not a 16-bit register"));
	$reg2= ($regnum16{$reg2} // croak("$reg2 is not a 16-bit register"));
	use integer;
	my $rex= (($reg1 & 8) >> 1) | (($reg2 & 8) >> 3);
	$self->{_buf} .= $rex?
		pack('CCCC', 0x66, 0x40|$rex, $opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7))
		: pack('CCC', 0x66, $opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7));
	$self;
}
sub _append_op8_reg_reg {
	my ($self, $opcode, $reg1, $reg2)= @_;
	use integer;
	$reg1= $regnum8{$reg1};
	$reg2= $regnum8{$reg2};
	# special case for the "high byte" registers.  They can't be used in an
	# instruction that uses the REX prefix.
	if (!defined $reg1 || !defined $reg2) {
		my $old_reg1= $reg1;
		my $old_reg2= $reg2;
		$reg1= $regnum8_high{$_[2]} // croak "$_[2] is not a valid 8-bit register";
		$reg2= $regnum8_high{$_[3]} // croak "$_[3] is not a valid 8-bit register";
		if (($old_reg1 && $old_reg1 > 3) || ($old_reg2 && $old_reg2 > 3)) {
			croak "Can't combine $_[2] with $_[3] in same instruction";
		}
		$self->{_buf} .= pack('CC', $opcode, 0xC0 | ($reg1 << 3) | $reg2);
	}
	else {
		$self->{_buf} .= ($reg1 > 3 || $reg2 > 3)?
			pack('CCC', 0x40|(($reg1 & 8) >> 1) | (($reg2 & 8) >> 3), $opcode, 0xC0 | (($reg1 & 7) << 3) | ($reg2 & 7))
			: pack('CC', $opcode, 0xC0 | ($reg1 << 3) | $reg2);
	}
	$self;
}

# Like above, but the first register argument isn't really a register argument
# and therefore doesn't require a 0x40 prefix for values > 3
sub _append_op8_opreg_reg {
	my ($self, $opcode, $opreg, $reg2)= @_;
	use integer;
	$reg2= $regnum8{$reg2};
	# special case for the "high byte" registers.  They can't be used in an
	# instruction that uses the REX prefix.
	if (!defined $reg2) {
		my $old_reg2= $reg2;
		$reg2= $regnum8_high{$_[3]} // croak "$_[3] is not a valid 8-bit register";
		$self->{_buf} .= pack('CC', $opcode, 0xC0 | ($opreg << 3) | $reg2);
	}
	else {
		$self->{_buf} .= ($reg2 > 3)?
			pack('CCC', 0x40| (($reg2 & 8) >> 3), $opcode, 0xC0 | ($opreg << 3) | ($reg2 & 7))
			: pack('CC', $opcode, 0xC0 | ($opreg << 3) | $reg2);
	}
	$self;
}

#=head2 _append_op##_reg_mem
#
#Encode standard ##-bit instruction with REX prefix which addresses memory for one of its operands.
#The encoded length might not be resolved until later if an unknown displacement value was given.
#
#=cut

sub _append_op64_reg_mem {
	my ($self, $rex, $opcode, $reg, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$reg= $regnum64{$reg} // croak "$reg is not a valid 64-bit register"
		if defined $reg;
	$base_reg= $regnum64{$base_reg} // croak "$base_reg is not a valid 64-bit register"
		if defined $base_reg;
	$index_reg= $regnum64{$index_reg} // croak "$index_reg is not a valid 64-bit register"
		if defined $index_reg;
	$self->_append_possible_unknown('_encode_op_reg_mem', [$rex, $opcode, $reg, $base_reg, $disp, $index_reg, $scale], 4, 7);
	$self;
}

sub _append_op32_reg_mem {
	my ($self, $rex, $opcode, $reg, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$reg= $regnum32{$reg} // croak "$reg is not a valid 32-bit register"
		if defined $reg;
	$base_reg= $regnum64{$base_reg} // croak "$base_reg is not a valid 64-bit register"
		if defined $base_reg;
	$index_reg= $regnum64{$index_reg} // croak "$index_reg is not a valid 64-bit register"
		if defined $index_reg;
	$self->_append_possible_unknown('_encode_op_reg_mem', [$rex, $opcode, $reg, $base_reg, $disp, $index_reg, $scale], 4, 7);
}

sub _append_op16_reg_mem {
	my ($self, $rex, $opcode, $reg, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$reg= $regnum16{$reg} // croak "$reg is not a valid 16-bit register"
		if defined $reg;
	$base_reg= $regnum64{$base_reg} // croak "$base_reg is not a valid 64-bit register"
		if defined $base_reg;
	$index_reg= $regnum64{$index_reg} // croak "$index_reg is not a valid 64-bit register"
		if defined $index_reg;
	$self->{_buf} .= "\x66";
	$self->_append_possible_unknown('_encode_op_reg_mem', [$rex, $opcode, $reg, $base_reg, $disp, $index_reg, $scale], 4, 7);
}

sub _append_op8_reg_mem {
	my ($self, $rex, $opcode, $reg, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= $regnum64{$base_reg} // croak "$base_reg is not a valid 64-bit register"
		if defined $base_reg;
	$index_reg= $regnum64{$index_reg} // croak "$index_reg is not a valid 64-bit register"
		if defined $index_reg;
	$reg= $regnum8{$reg};
	# special case for the "high byte" registers
	if (!defined $reg) {
		$reg= $regnum8_high{$_[3]} // croak "$_[3] is not a valid 8-bit register";
		!$rex && ($base_reg//0) < 8 && ($index_reg//0) < 8
			or croak "Cannot use $_[3] in instruction with REX prefix";
	}
	# special case for needing REX byte for SPL, BPL, DIL, and SIL
	elsif ($reg > 3) {
		$rex |= 0x40;
	}
	$self->_append_possible_unknown('_encode_op_reg_mem', [$rex, $opcode, $reg, $base_reg, $disp, $index_reg, $scale], 4, 7);
}
# Like above, but the first register is a constant and don't need to test it for
# requiring a REX prefix if >3.
sub _append_op8_opreg_mem {
	my ($self, $rex, $opcode, $opreg, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= $regnum64{$base_reg} // croak "$base_reg is not a valid 64-bit register"
		if defined $base_reg;
	$index_reg= $regnum64{$index_reg} // croak "$index_reg is not a valid 64-bit register"
		if defined $index_reg;
	$self->_append_possible_unknown('_encode_op_reg_mem', [$rex, $opcode, $opreg, $base_reg, $disp, $index_reg, $scale], 4, 7);
}

#=head2 _append_op##_const_to_mem
#
#Encode standard ##-bit instruction with REX prefix which operates on a constant and then
#writes to a memory location.
#
#=cut

sub _append_op8_const_to_mem {
	my ($self, $opcode, $opreg, $value, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= ($regnum64{$base_reg} // croak "$base_reg is not a 64-bit register")
		if defined $base_reg;
	$index_reg= ($regnum64{$index_reg} // croak "$index_reg is not a 64-bit register")
		if defined $index_reg;
	$self->_append_possible_unknown('_encode_op_reg_mem', [ 0, $opcode, $opreg, $base_reg, $disp, $index_reg, $scale, 'C', $value ], ref $disp? 4 : 8, defined $disp? 16:12);
}
sub _append_op16_const_to_mem {
	my ($self, $opcode, $opreg, $value, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= ($regnum64{$base_reg} // croak "$base_reg is not a 64-bit register")
		if defined $base_reg;
	$index_reg= ($regnum64{$index_reg} // croak "$index_reg is not a 64-bit register")
		if defined $index_reg;
	$self->{_buf} .= "\x66";
	$self->_append_possible_unknown('_encode_op_reg_mem', [ 0, $opcode, $opreg, $base_reg, $disp, $index_reg, $scale, 'v', $value ], ref $disp? 4 : 8, defined $disp? 16:12);
}
sub _append_op32_const_to_mem {
	my ($self, $opcode, $opreg, $value, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= ($regnum64{$base_reg} // croak "$base_reg is not a 64-bit register")
		if defined $base_reg;
	$index_reg= ($regnum64{$index_reg} // croak "$index_reg is not a 64-bit register")
		if defined $index_reg;
	$self->_append_possible_unknown('_encode_op_reg_mem', [ 0, $opcode, $opreg, $base_reg, $disp, $index_reg, $scale, 'V', $value ], ref $disp? 4 : 8, defined $disp? 16:12);
}
sub _append_op64_const_to_mem {
	my ($self, $opcode, $opreg, $value, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= ($regnum64{$base_reg} // croak "$base_reg is not a 64-bit register")
		if defined $base_reg;
	$index_reg= ($regnum64{$index_reg} // croak "$index_reg is not a 64-bit register")
		if defined $index_reg;
	$self->_append_possible_unknown('_encode_op_reg_mem', [ 8, $opcode, $opreg, $base_reg, $disp, $index_reg, $scale, 'V', $value ], ref $disp? 4 : 8, defined $disp? 16:12);
}


# scale values for the SIB byte
my %SIB_scale= (
	1 => 0x00,
	2 => 0x40,
	4 => 0x80,
	8 => 0xC0
);

sub _encode_op_reg_mem {
	my ($self, $rex, $opcode, $reg, $base_reg, $disp, $index_reg, $scale, $immed_pack, $immed)= @_;
	use integer;
	$rex |= ($reg & 8) >> 1;

	my $tail;
	if (defined $base_reg) {
		$rex |= ($base_reg & 8) >> 3;

		# RBP,R13 always gets mod_rm displacement to differentiate from Null base register
		my ($mod_rm, $suffix)= !$disp? ( ($base_reg&7) == 5? (0x40, "\0") : (0x00, '') )
			: (($disp >>  7) == ($disp >>  8))? (0x40, pack('c', $disp))
			: (($disp >> 31) == ($disp >> 32))? (0x80, pack('V', $disp))
			: croak "address displacement out of range: $disp";

		if (defined $index_reg) {
			my $scale= $SIB_scale{$scale // 1} // croak "invalid index multiplier $scale";
			$index_reg != 4 or croak "RSP cannot be used as index register";
			$rex |= ($index_reg & 8) >> 2;
			$tail= pack('CC', $mod_rm | (($reg & 7) << 3) | 4, $scale | (($index_reg & 7) << 3) | ($base_reg & 7)) . $suffix;
		}
		# RSP,R12 always gets a SIB byte
		elsif (($base_reg&7) == 4) {
			$tail= pack('CC', $mod_rm | (($reg & 7) << 3) | 4, 0x24) . $suffix;
		}
		else {
			# Null index register is encoded as RSP
			$tail= pack('C', $mod_rm | (($reg & 7) << 3) | ($base_reg & 7)) . $suffix;
		}
	} else {
		# Null base register is encoded as RBP + 32bit displacement

		(($disp >> 31) == ($disp >> 32))
			or croak "address displacement out of range: $disp";

		if (defined $index_reg) {
			my $scale= $SIB_scale{$scale // 1} // croak "invalid index multiplier $scale";
			$index_reg != 4 or croak "RSP cannot be used as index register";
			$rex |= ($index_reg & 8) >> 2;
			$tail= pack('CCV', (($reg & 7) << 3) | 4, $scale | (($index_reg & 7) << 3) | 5, $disp);
		}
		else {
			# Null index register is encoded as RSP
			$tail= pack('CCV', (($reg & 7) << 3) | 4, 0x25, $disp);
		}
	}
	$tail .= pack($immed_pack, $immed)
		if defined $immed;

	return $rex?
		pack('CC', ($rex|0x40), $opcode) . $tail
		: pack('C', $opcode) . $tail;
}

#=head2 _append_mathopNN_const
#
#This is so bizarre I don't even know where to start.  Most "math-like" instructions have an opcode
#for an immediate the size of the register (except 64-bit which only gets a 32-bit immediate), an
#opcode for an 8-bit immediate, and another opcode specifically for the AX register which is a byte
#shorter than the normal, which is the only redeeming reason to bother using it.
#Also, there is a constant stored in the 3 bits of the unused register in the ModRM byte which acts
#as an extension of the opcode.
#
#These 4 methods are the generic implementation for encoding this mess.
#Each implementation also handles the possibility that the immediate value is an unknown variable
#resolved while the instructions are assembled.
#
#=over
#
#=item C<_append_mathop64_const($opcodeAX32, $opcode8, $opcode32, $opcode_reg, $reg, $immed)>
#
#This one is annoying because it only gets a sign-extended 32-bit value, so you actually only get
#31 bits of an immediate value for a 64-bit instruction.
#
#=cut

sub _append_mathop64_const {
	my ($self, @args)= @_; # $opcodeAX32, $opcode8, $opcode32, $opcode_reg, $reg, $immed
	$args[4]= $regnum64{$args[4]} // croak("$args[4] is not a 64-bit register");
	$self->_append_possible_unknown('_encode_mathop64_imm', \@args, 5, 7);
}
sub _encode_mathop64_imm {
	my ($self, $opcodeAX32, $opcode8, $opcode32, $opcode_reg, $reg, $value)= @_;
	use integer;
	my $rex= 0x48 | (($reg & 8)>>3);
	defined $opcode8 && (($value >> 7) == ($value >> 8))?
		pack('CCCc', $rex, $opcode8, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value)
	: (($value >> 31) == ($value >> 32))? (
		# Ops on AX get encoded as a special instruction
		$reg? pack('CCCV', $rex, $opcode32, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value)
			: pack('CCV', $rex, $opcodeAX32, $value)
	)
	# 64-bit only supports 32-bit sign-extend immediate
	: croak "$value is wider than 32-bit";
}

#=item C<_append_mathop32_const($opcodeAX32, $opcode8, $opcode32, $opcode_reg, $reg, $immed)>
#
#=cut

sub _append_mathop32_const {
	my ($self, @args)= @_; # $opcodeAX32, $opcode8, $opcode32, $opcode_reg, $reg, $immed
	$args[4]= $regnum32{$args[4]} // croak("$args[4] is not a 32-bit register");
	$self->_append_possible_unknown('_encode_mathop32_imm', \@args, 5, 7);
}
sub _encode_mathop32_imm {
	my ($self, $opcodeAX32, $opcode8, $opcode32, $opcode_reg, $reg, $value)= @_;
	use integer;
	my $rex= (($reg & 8)>>3);
	defined $opcode8 && (($value >> 7) == ($value >> 8) or ($value >> 8 == 0xFFFFFF))?
		(	$rex? pack('CCCC', 0x40|$rex, $opcode8, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value&0xFF)
				: pack('CCC', $opcode8, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value&0xFF)
		)
		: (($value >> 32) == ($value >> 33))? (
			# Ops on AX get encoded as a special instruction
			$rex? pack('CCCV', 0x40|$rex, $opcode32, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value)
			: $reg? pack('CCV', $opcode32, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value)
			: pack('CV', $opcodeAX32, $value)
		)
		: croak "$value is wider than 32-bit";
}

#=item C<_append_mathop16_const($opcodeAX16, $opcode8, $opcode16, $opcode_reg, $reg, $immed)>
#
#=cut

sub _append_mathop16_const {
	my ($self, @args)= @_; # $opcodeAX16, $opcode8, $opcode16, $opcode_reg, $reg, $immed
	$args[4]= $regnum16{$args[4]} // croak("$args[4] is not a 16-bit register");
	$self->_append_possible_unknown('_encode_mathop16_imm', \@args, 5, 8);
}
sub _encode_mathop16_imm {
	my ($self, $opcodeAX16, $opcode8, $opcode16, $opcode_reg, $reg, $value)= @_;
	use integer;
	my $rex= (($reg & 8)>>3);
	defined $opcode8 && (($value >> 7) == ($value >> 8) or ($value >> 8 == 0xFF))?
		(	$rex? pack('CCCCC', 0x66, 0x40|$rex, $opcode8, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value&0xFF)
				: pack('CCCC', 0x66, $opcode8, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value&0xFF)
		)
		: (($value >> 16) == ($value >> 17))? (
			# Ops on AX get encoded as a special instruction
			$rex? pack('CCCCv', 0x66, 0x40|$rex, $opcode16, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value&0xFFFF)
			: $reg? pack('CCCv', 0x66, $opcode16, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value&0xFFFF)
			: pack('CCv', 0x66, $opcodeAX16, $value)
		)
		: croak "$value is wider than 16-bit";
}

#=item C<_append_mathop8_const($opcodeAX8, $opcode8, $opcode_reg, $reg, $immed)>
#
#On the upside, this one only has one bit width, so the length of the instruction is known even if
#the immediate value isn't.
#
#However, we also have to handle the case where "dil", "sil", etc need a REX prefix but AH, BH, etc
#can't have one.
#
#=back
#
#=cut

sub _append_mathop8_const {
	my ($self, $opcodeAX8, $opcode8, $opcode_reg, $reg, $immed)= @_;
	use integer;
	$reg= $regnum8{$reg};
	my $value= ref $immed? 0x00 : $immed;
	(($value >> 8) == ($value >> 9)) or croak "$value is wider than 8 bits";
	if (!defined $reg) {
		$reg= $regnum8_high{$_[1]} // croak("$reg is not a 8-bit register");
		$self->{_buf} .= pack('CCC', $opcode8, 0xC0 | ($opcode_reg<<3) | ($reg & 7), $value&0xFF);
	} elsif (!$reg) {
		$self->{_buf} .= pack('CC', $opcodeAX8, $value&0xFF);
	} elsif ($reg > 3) {
		$self->{_buf} .= pack('CCCC', 0x40|(($reg & 8)>>3), $opcode8, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value&0xFF);
	} else {
		$self->{_buf} .= pack('CCC', $opcode8, 0xC0 | ($opcode_reg << 3) | ($reg & 7), $value&0xFF);
	}
	$self->_mark_unresolved(-1, encode => '_repack', bits => 8, value => $immed)
		if ref $immed;
	$self;
}

sub _append_mathop64_const_to_mem {
	my ($self, $opcode8, $opcode32, $opcode_reg, $value, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= ($regnum64{$base_reg} // croak "$base_reg is not a 64-bit register")
		if defined $base_reg;
	$index_reg= ($regnum64{$index_reg} // croak "$index_reg is not a 64-bit register")
		if defined $index_reg;
	$self->_append_possible_unknown('_encode_mathop64_mem_immed', [ $opcode8, $opcode32, $opcode_reg, $value, $base_reg, $disp, $index_reg, $scale ], 3, defined $disp? 9:12);
}
sub _encode_mathop64_mem_immed {
	my ($self, $opcode8, $opcode32, $opcode_reg, $value, $base_reg, $disp, $index_reg, $scale)= @_;
	use integer;
	defined $opcode8 && (($value >> 7) == ($value >> 8))?
		$self->_encode_op_reg_mem(8, $opcode8, $opcode_reg, $base_reg, $disp, $index_reg, $scale, 'C', $value&0xFF)
	: (($value >> 31) == ($value >> 32))?
		$self->_encode_op_reg_mem(8, $opcode32, $opcode_reg, $base_reg, $disp, $index_reg, $scale, 'V', $value&0xFFFFFFFF)
	: croak "$value is wider than 31-bit";
}

sub _append_mathop32_const_to_mem {
	my ($self, $opcode8, $opcode32, $opcode_reg, $value, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= ($regnum64{$base_reg} // croak "$base_reg is not a 64-bit register")
		if defined $base_reg;
	$index_reg= ($regnum64{$index_reg} // croak "$index_reg is not a 64-bit register")
		if defined $index_reg;
	$self->_append_possible_unknown('_encode_mathop32_mem_immed', [ $opcode8, $opcode32, $opcode_reg, $value, $base_reg, $disp, $index_reg, $scale ], 3, defined $disp? 12:8);
}
sub _encode_mathop32_mem_immed {
	my ($self, $opcode8, $opcode32, $opcode_reg, $value, $base_reg, $disp, $index_reg, $scale)= @_;
	use integer;
	defined $opcode8 && (($value >> 7) == ($value >> 8) or ($value >> 8 == 0xFFFFFF))?
		$self->_encode_op_reg_mem(0, $opcode8, $opcode_reg, $base_reg, $disp, $index_reg, $scale).pack('C',$value&0xFF)
	: (($value >> 32) == ($value >> 33))?
		$self->_encode_op_reg_mem(0, $opcode32, $opcode_reg, $base_reg, $disp, $index_reg, $scale).pack('V', $value&0xFFFFFFFF)
	: croak "$value is wider than 32-bit";
}

sub _append_mathop16_const_to_mem {
	my ($self, $opcode8, $opcode16, $opcode_reg, $value, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= ($regnum64{$base_reg} // croak "$base_reg is not a 64-bit register")
		if defined $base_reg;
	$index_reg= ($regnum64{$index_reg} // croak "$index_reg is not a 64-bit register")
		if defined $index_reg;
	$self->{_buf} .= "\x66";
	$self->_append_possible_unknown('_encode_mathop16_mem_immed', [ $opcode8, $opcode16, $opcode_reg, $value, $base_reg, $disp, $index_reg, $scale ], 3, defined $disp? 10:6);
}
sub _encode_mathop16_mem_immed {
	my ($self, $opcode8, $opcode16, $opcode_reg, $value, $base_reg, $disp, $index_reg, $scale)= @_;
	use integer;
	defined $opcode8 && (($value >> 7) == ($value >> 8) or ($value >> 8 == 0xFF))?
		$self->_encode_op_reg_mem(0, $opcode8, $opcode_reg, $base_reg, $disp, $index_reg, $scale).pack('C',$value&0xFF)
	: (($value >> 16) == ($value >> 17))?
		$self->_encode_op_reg_mem(0, $opcode16, $opcode_reg, $base_reg, $disp, $index_reg, $scale).pack('v', $value&0xFFFF)
	: croak "$value is wider than 16-bit";
}

sub _append_mathop8_const_to_mem {
	my ($self, $opcode8, $opcode_reg, $value, $mem)= @_;
	my ($base_reg, $disp, $index_reg, $scale)= @$mem;
	$base_reg= ($regnum64{$base_reg} // croak "$base_reg is not a 64-bit register")
		if defined $base_reg;
	$index_reg= ($regnum64{$index_reg} // croak "$index_reg is not a 64-bit register")
		if defined $index_reg;
	$self->_append_possible_unknown('_encode_mathop8_mem_immed', [ $opcode8, $opcode_reg, $value, $base_reg, $disp, $index_reg, $scale ], 2, defined $disp? 10:6);
}
sub _encode_mathop8_mem_immed {
	my ($self, $opcode8, $opcode_reg, $value, $base_reg, $disp, $index_reg, $scale)= @_;
	use integer;
	(($value >> 8) == ($value >> 9)) or croak "$value is wider than 8 bit";
	$self->_encode_op_reg_mem(0, $opcode8, $opcode_reg, $base_reg, $disp, $index_reg, $scale).pack('C',$value&0xFF);
}

#=head2 C<_append_shiftop_reg_imm( $bitwidth, $opcode_1, $opcode_imm, $opreg, $reg, $immed )>
#
#Shift instructions often have a special case for shifting by 1.  This utility method
#selects that opcode if the immediate value is 1.
#
#It also allows the immediate to be an expression, though I doubt that will ever happen...
#Immediate values are always a single byte, and the processor masks them to 0..63
#so the upper bits are irrelevant.
#
#=cut

sub _append_shiftop_reg_imm {
	my ($self, $bits, $opcode_sh1, $opcode_imm, $opreg, $reg, $immed)= @_;

	# Select appropriate opcode
	my $op= $immed eq 1? $opcode_sh1 : $opcode_imm;

	$bits == 64?   $self->_append_op64_reg_reg($op, $opreg, $reg)
	: $bits == 32? $self->_append_op32_reg_reg($op, $opreg, $reg)
	: $bits == 16? $self->_append_op16_reg_reg($op, $opreg, $reg)
	:              $self->_append_op8_opreg_reg($op, $opreg, $reg);

	# If not using the shift-one opcode, append an immediate byte.
	unless ($immed eq 1) {
		$self->{_buf} .= pack('C', ref $immed? 0 : $immed);
		$self->_mark_unresolved(-1, encode => '_repack', bits => 8, value => $immed)
			if ref $immed;
	}

	$self;
}

#=head2 _append_shiftop_mem_imm
#
#Same as above, for memory locations
#
#=cut

sub _append_shiftop_mem_imm {
	my ($self, $bits, $opcode_sh1, $opcode_imm, $opreg, $mem, $immed)= @_;

	# Select appropriate opcode
	my $op= $immed eq 1? $opcode_sh1 : $opcode_imm;

	$bits == 64?   $self->_append_op64_reg_mem(8, $op, $opreg, $mem)
	: $bits == 32? $self->_append_op32_reg_mem(0, $op, $opreg, $mem)
	: $bits == 16? $self->_append_op16_reg_mem(0, $op, $opreg, $mem)
	:              $self->_append_op8_opreg_mem(0, $op, $opreg, $mem);

	# If not using the shift-one opcode, append an immediate byte.
	unless ($immed eq 1) {
		$self->{_buf} .= pack('C', ref $immed? 0 : $immed);
		$self->_mark_unresolved(-1, encode => '_repack', bits => 8, value => $immed)
			if ref $immed;
	}

	$self;
}

#=head2 C<_append_jmp_cond($cond_code, $label)>
#
#Appends a conditional jump instruction, which is either the short 2-byte form for 8-bit offsets,
#or 6 bytes for jumps of 32-bit offsets.  The implementation optimistically assumes the 2-byte
#length until L is called, when the actual length will be determined.
#
#Returns $self, for chaining.
#
#=cut

sub _append_jmp_cond {
	$_[2]= $_[0]->get_label unless defined $_[2];

	my ($self, $cond, $label)= @_;
	use integer;
	$label= $self->get_label($label)
		unless ref $label;
	$self->_mark_unresolved(
		2, # estimated length
		encode => sub {
			my ($self, $params)= @_;
			defined $label->{offset} or croak "Label $label is not marked";
			my $ofs= $label->{offset} - ($params->{offset}+$params->{len});
			my $short= (($ofs>>7) == ($ofs>>8));
			return $short?
				pack('Cc', 0x70 + $cond, $ofs)
				: pack('CCV', 0x0F, 0x80 + $cond, $ofs);
		}
	);
	$self;
}

#=head2 C<_append_jmp_cx($opcode, $label)>
#
#Appends one of the special CX-related jumps (like L).  These can only have an 8-bit offset
#and are fixed-length.
#
#=cut

sub _append_jmp_cx {
	my ($self, $op, $label)= @_;
	use integer;
	$label= $self->get_label($label)
		unless ref $label;
	$self->_mark_unresolved(
		2, # estimated length
		encode => sub {
			my ($self, $params)= @_;
			defined $label->{offset} or croak "Label $label is not marked";
			my $ofs= $label->{offset} - ($params->{offset}+$params->{len});
			(($ofs>>7) == ($ofs>>8)) or croak "Label too far, can only short-jump";
			return pack('Cc', $op, $ofs);
		}
	);
	return $self;
}

sub _append_possible_unknown {
	my ($self, $encoder, $encoder_args, $unknown_pos, $estimated_length)= @_;
	my $u= $encoder_args->[$unknown_pos];
	if (ref $u && ref $u ne 'SCALAR') {
		ref($u)->can('value')
			or croak "Expected object with '->value' method";
		$self->_mark_unresolved(
			$estimated_length,
			encode => sub {
				my $self= shift;
				my @args= @$encoder_args;
				$args[$unknown_pos]= $u->value
					// croak "Value '$u->{name}' is still unresolved";
				$self->$encoder(@args);
			},
		);
	}
	else {
		$self->{_buf} .= $self->$encoder(@$encoder_args);
	}
	$self;
}

#=head2 C<_mark_unresolved($location, encode => sub {...}, %other)>
#
#Creates a new unresolved marker in the instruction stream, indicating things which can't be known
#until the entire instruction stream is written. (such as jump instructions).
#
#The parameters 'offset' and 'len' will be filled in automatically based on the $location parameter.
#If C<$location> is negative, it indicates offset is that many bytes backward from the end of the
#buffer.  If C<$location> is positive, it means the unresolved symbol hasn't been written yet and
#the 'offset' will be the current end of the buffer and 'len' is the value of $location.
#
#The other usual (but not required) parameter is 'encode'.  This references a method callback which
#will return the encoded instruction (or die, if there is still not enough information to do so).
#
#All C<%other> parameters are passed to the callback as a HASHREF.
#
#=cut

sub _mark_unresolved {
	my ($self, $location)= (shift, shift);
	my $offset= length($self->{_buf});

	# If location is negative, move the 'offset' back that many bytes.
	# The length is the abs of location.
	if ($location < 0) {
		$location= -$location;
		$offset -= $location;
	}
	# If the location is positive, offset is the end of the string.
	# Add padding bytes for the length of the instruction.
	else {
		$self->{_buf} .= "\0" x $location;
	}

	if ($self->{debug}) {
		my ($i, @caller);
		# Walk up stack until the entry-point method
		while (@caller= caller(++$i)) {
			last if $caller[0] ne __PACKAGE__;
		}
		push @_, caller => \@caller;
	}
	#print "Unresolved at $offset ($location)\n";
	push @{ $self->_unresolved }, { offset => $offset, len => $location, @_ };
}

sub _repack {
	my ($self, $params)= @_;
	use integer;
	my $v= $params->{value}->value;
	defined $v or croak "Placeholder $params->{value} has not been assigned";
	my $bits= $params->{bits};
	my $pack= $bits <= 8? 'C' : $bits <= 16? 'v' : $bits <= 32? 'V' : $bits <= 64? 'Q<' : die "Unhandled bits $bits\n";
	$bits == 64 || (($v >> $bits) == ($v >> ($bits+1))) or croak "$v is wider than $bits bits";
	return pack($pack, $v & ~(~0 << $bits));
}

#=head2 C<_resovle>
#
#This is the algorithm that resolves the unresolved instructions.  It takes an iterative approach
#that is relatively efficient as long as the predicted lengths of the unresolved instructions are
#correct.  If many instructions guess the wrong length then this could get slow for very long
#instruction strings.
#
#=cut

sub _resolve {
	my $self= shift;

	# We repeat the process any time something changed length
	my $changed_len= 1;
	while ($changed_len) {
		$changed_len= 0;

		# Track the amount we have shifted the current instruction in $ofs
		my $ofs= 0;
		for my $p (@{ $self->_unresolved }) {
			#print "Shifting $p by $ofs\n" if $ofs;
			$p->{offset} += $ofs if $ofs;

			# Ignore things without an 'encode' callback (like labels)
			my $fn= $p->{encode}
				or next;

			# Get new encoding, then replace those bytes in the instruction string
			eval {
				my $enc= $self->$fn($p);
				substr($self->{_buf}, $p->{offset}, $p->{len})= $enc;

				# If the length changed, update $ofs and current ->len
				if (length($enc) != $p->{len}) {
					#print "New size is ".length($enc)."\n";
					$changed_len= 1;
					$ofs += (length($enc) - $p->{len});
					$p->{len}= length($enc);
				}
			};
			if ($@) {
				if ($p->{caller}) {
					croak "Failed to encode instruction $p->{caller}[3] from $p->{caller}[1] line $p->{caller}[2]:\n   $@";
				} else {
					croak "Failed to encode instruction (enable diagnostics with ->debug(1) ): $@";
				}
			}
		}
	}
}

1;

__END__